/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. * * Author: Ajit Kumar Pandey <[email protected]> */ #ifndef __SOF_AMD_ACP_H #define __SOF_AMD_ACP_H #include <linux/dmi.h> #include <linux/soundwire/sdw_amd.h> #include "../sof-priv.h" #include "../sof-audio.h" #define ACP_MAX_STREAM … #define ACP_DSP_BAR … #define ACP_HW_SEM_RETRY_COUNT … #define ACP_REG_POLL_INTERVAL … #define ACP_REG_POLL_TIMEOUT_US … #define ACP_DMA_COMPLETE_TIMEOUT_US … #define ACP_PGFSM_CNTL_POWER_ON_MASK … #define ACP_PGFSM_STATUS_MASK … #define ACP_POWERED_ON … #define ACP_ASSERT_RESET … #define ACP_RELEASE_RESET … #define ACP_SOFT_RESET_DONE_MASK … #define ACP_DSP_ASSERT_RESET … #define ACP_DSP_RELEASE_RESET … #define ACP_DSP_SOFT_RESET_DONE_MASK … #define ACP_DSP_INTR_EN_MASK … #define ACP3X_SRAM_PTE_OFFSET … #define ACP5X_SRAM_PTE_OFFSET … #define ACP6X_SRAM_PTE_OFFSET … #define PAGE_SIZE_4K_ENABLE … #define ACP_PAGE_SIZE … #define ACP_DMA_CH_RUN … #define ACP_MAX_DESC_CNT … #define DSP_FW_RUN_ENABLE … #define ACP_SHA_RUN … #define ACP_SHA_RESET … #define ACP_SHA_HEADER … #define ACP_DMA_CH_RST … #define ACP_DMA_CH_GRACEFUL_RST_EN … #define ACP_ATU_CACHE_INVALID … #define ACP_MAX_DESC … #define ACPBUS_REG_BASE_OFFSET … #define ACP_DEFAULT_DRAM_LENGTH … #define ACP3X_SCRATCH_MEMORY_ADDRESS … #define ACP_SYSTEM_MEMORY_WINDOW … #define ACP_IRAM_BASE_ADDRESS … #define ACP_DRAM_BASE_ADDRESS … #define ACP_DRAM_PAGE_COUNT … #define ACP_SRAM_BASE_ADDRESS … #define ACP_DSP_TO_HOST_IRQ … #define ACP_RN_PCI_ID … #define ACP_VANGOGH_PCI_ID … #define ACP_RMB_PCI_ID … #define ACP63_PCI_ID … #define HOST_BRIDGE_CZN … #define HOST_BRIDGE_VGH … #define HOST_BRIDGE_RMB … #define HOST_BRIDGE_ACP63 … #define ACP_SHA_STAT … #define ACP_PSP_TIMEOUT_US … #define ACP_EXT_INTR_ERROR_STAT … #define MP0_C2PMSG_114_REG … #define MP0_C2PMSG_73_REG … #define MBOX_ACP_SHA_DMA_COMMAND … #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND … #define MBOX_DELAY_US … #define MBOX_READY_MASK … #define MBOX_STATUS_MASK … #define MBOX_ISREADY_FLAG … #define IRAM_DRAM_FENCE_0 … #define IRAM_DRAM_FENCE_1 … #define IRAM_DRAM_FENCE_2 … #define BOX_SIZE_512 … #define BOX_SIZE_1024 … #define EXCEPT_MAX_HDR_SIZE … #define AMD_STACK_DUMP_SIZE … #define SRAM1_SIZE … #define PROBE_STATUS_BIT … #define ACP_FIRMWARE_SIGNATURE … #define ACP_ERROR_IRQ_MASK … #define ACP_SDW0_IRQ_MASK … #define ACP_SDW1_IRQ_MASK … #define SDW_ACPI_ADDR_ACP63 … #define ACP_DEFAULT_SRAM_LENGTH … #define ACP_SRAM_PAGE_COUNT … #define ACP6X_SDW_MAX_MANAGER_COUNT … enum clock_source { … }; struct acp_atu_grp_pte { … }; dma_tx_cnt; struct dma_descriptor { … }; /* Scratch memory structure for communication b/w host and dsp */ struct scratch_ipc_conf { … }; struct scratch_reg_conf { … }; struct acp_dsp_stream { … }; struct sof_amd_acp_desc { … }; struct acp_quirk_entry { … }; /* Common device data struct for ACP devices */ struct acp_dev_data { … }; void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, unsigned int dest_addr, int dsp_data_size); int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, unsigned int start_addr, unsigned int dest_addr, unsigned int image_length); /* ACP device probe/remove */ int amd_sof_acp_probe(struct snd_sof_dev *sdev); void amd_sof_acp_remove(struct snd_sof_dev *sdev); /* DSP Loader callbacks */ int acp_sof_dsp_run(struct snd_sof_dev *sdev); int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); /* Block IO callbacks */ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, u32 offset, void *src, size_t size); int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, u32 offset, void *dest, size_t size); /* IPC callbacks */ irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, void *p, size_t sz); int acp_set_stream_data_offset(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, size_t posn_offset); int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); /* ACP - DSP stream callbacks */ int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); int acp_dsp_stream_init(struct snd_sof_dev *sdev); struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); /* * DSP PCM Operations. */ int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_sof_platform_stream_params *platform_params); snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); extern const struct snd_sof_dsp_ops sof_acp_common_ops; extern struct snd_sof_dsp_ops sof_renoir_ops; int sof_renoir_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_vangogh_ops; int sof_vangogh_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_rembrandt_ops; int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_acp63_ops; int sof_acp63_ops_init(struct snd_sof_dev *sdev); struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); /* Machine configuration */ int snd_amd_acp_find_config(struct pci_dev *pci); /* Trace */ int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, struct sof_ipc_dma_trace_params_ext *dtrace_params); int acp_sof_trace_release(struct snd_sof_dev *sdev); /* PM Callbacks */ int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); int amd_sof_acp_resume(struct snd_sof_dev *sdev); void amd_sof_ipc_dump(struct snd_sof_dev *sdev); void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) { … } int acp_probes_register(struct snd_sof_dev *sdev); void acp_probes_unregister(struct snd_sof_dev *sdev); extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; extern const struct dmi_system_id acp_sof_quirk_table[]; #endif
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