linux/drivers/clk/renesas/rcar-gen2-cpg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R-Car Gen2 Clock Pulse Generator
 *
 * Copyright (C) 2016 Cogent Embedded Inc.
 */

#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"

#define CPG_FRQCRB …
#define CPG_FRQCRB_KICK …
#define CPG_SDCKCR …
#define CPG_PLL0CR …
#define CPG_PLL0CR_STC_SHIFT …
#define CPG_PLL0CR_STC_MASK …
#define CPG_FRQCRC …
#define CPG_FRQCRC_ZFC_SHIFT …
#define CPG_FRQCRC_ZFC_MASK …
#define CPG_ADSPCKCR …
#define CPG_RCANCKCR …

static DEFINE_SPINLOCK(cpg_lock);

/*
 * Z Clock
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
 * parent - fixed parent.  No clk_set_parent support
 */

struct cpg_z_clk { … };

#define to_z_clk(_hw) …

static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static int cpg_z_clk_determine_rate(struct clk_hw *hw,
				    struct clk_rate_request *req)
{ … }

static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{ … }

static const struct clk_ops cpg_z_clk_ops = …;

static struct clk * __init cpg_z_clk_register(const char *name,
					      const char *parent_name,
					      void __iomem *base)
{ … }

static struct clk * __init cpg_rcan_clk_register(const char *name,
						 const char *parent_name,
						 void __iomem *base)
{ … }

/* ADSP divisors */
static const struct clk_div_table cpg_adsp_div_table[] = …;

static struct clk * __init cpg_adsp_clk_register(const char *name,
						 const char *parent_name,
						 void __iomem *base)
{ … }

/* SDHI divisors */
static const struct clk_div_table cpg_sdh_div_table[] = …;

static const struct clk_div_table cpg_sd01_div_table[] = …;

static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
static unsigned int cpg_pll0_div __initdata;
static u32 cpg_mode __initdata;
static u32 cpg_quirks __initdata;

#define SD_SKIP_FIRST …

static const struct soc_device_attribute cpg_quirks_match[] __initconst = …;

struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
	struct clk **clks, void __iomem *base,
	struct raw_notifier_head *notifiers)
{ … }

int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
			      unsigned int pll0_div, u32 mode)
{ … }