// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014-2015 Broadcom Corporation #include <linux/clk.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/slab.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> #include "cygnus-ssp.h" #define DEFAULT_VCO … #define CAPTURE_FCI_ID_BASE … #define CYGNUS_SSP_TRISTATE_MASK … #define CYGNUS_PLLCLKSEL_MASK … /* Used with stream_on field to indicate which streams are active */ #define PLAYBACK_STREAM_MASK … #define CAPTURE_STREAM_MASK … #define I2S_STREAM_CFG_MASK … #define I2S_CAP_STREAM_CFG_MASK … #define SPDIF_STREAM_CFG_MASK … #define CH_GRP_STEREO … /* Begin register offset defines */ #define AUD_MISC_SEROUT_OE_REG_BASE … #define AUD_MISC_SEROUT_SPDIF_OE … #define AUD_MISC_SEROUT_MCLK_OE … #define AUD_MISC_SEROUT_LRCK_OE … #define AUD_MISC_SEROUT_SCLK_OE … #define AUD_MISC_SEROUT_SDAT_OE … /* AUD_FMM_BF_CTRL_xxx regs */ #define BF_DST_CFG0_OFFSET … #define BF_DST_CFG1_OFFSET … #define BF_DST_CFG2_OFFSET … #define BF_DST_CTRL0_OFFSET … #define BF_DST_CTRL1_OFFSET … #define BF_DST_CTRL2_OFFSET … #define BF_SRC_CFG0_OFFSET … #define BF_SRC_CFG1_OFFSET … #define BF_SRC_CFG2_OFFSET … #define BF_SRC_CFG3_OFFSET … #define BF_SRC_CTRL0_OFFSET … #define BF_SRC_CTRL1_OFFSET … #define BF_SRC_CTRL2_OFFSET … #define BF_SRC_CTRL3_OFFSET … #define BF_SRC_GRP0_OFFSET … #define BF_SRC_GRP1_OFFSET … #define BF_SRC_GRP2_OFFSET … #define BF_SRC_GRP3_OFFSET … #define BF_SRC_GRP_EN_OFFSET … #define BF_SRC_GRP_FLOWON_OFFSET … #define BF_SRC_GRP_SYNC_DIS_OFFSET … /* AUD_FMM_IOP_OUT_I2S_xxx regs */ #define OUT_I2S_0_STREAM_CFG_OFFSET … #define OUT_I2S_0_CFG_OFFSET … #define OUT_I2S_0_MCLK_CFG_OFFSET … #define OUT_I2S_1_STREAM_CFG_OFFSET … #define OUT_I2S_1_CFG_OFFSET … #define OUT_I2S_1_MCLK_CFG_OFFSET … #define OUT_I2S_2_STREAM_CFG_OFFSET … #define OUT_I2S_2_CFG_OFFSET … #define OUT_I2S_2_MCLK_CFG_OFFSET … /* AUD_FMM_IOP_OUT_SPDIF_xxx regs */ #define SPDIF_STREAM_CFG_OFFSET … #define SPDIF_CTRL_OFFSET … #define SPDIF_FORMAT_CFG_OFFSET … #define SPDIF_MCLK_CFG_OFFSET … /* AUD_FMM_IOP_PLL_0_xxx regs */ #define IOP_PLL_0_MACRO_OFFSET … #define IOP_PLL_0_MDIV_Ch0_OFFSET … #define IOP_PLL_0_MDIV_Ch1_OFFSET … #define IOP_PLL_0_MDIV_Ch2_OFFSET … #define IOP_PLL_0_ACTIVE_MDIV_Ch0_OFFSET … #define IOP_PLL_0_ACTIVE_MDIV_Ch1_OFFSET … #define IOP_PLL_0_ACTIVE_MDIV_Ch2_OFFSET … /* AUD_FMM_IOP_xxx regs */ #define IOP_PLL_0_CONTROL_OFFSET … #define IOP_PLL_0_USER_NDIV_OFFSET … #define IOP_PLL_0_ACTIVE_NDIV_OFFSET … #define IOP_PLL_0_RESET_OFFSET … /* AUD_FMM_IOP_IN_I2S_xxx regs */ #define IN_I2S_0_STREAM_CFG_OFFSET … #define IN_I2S_0_CFG_OFFSET … #define IN_I2S_1_STREAM_CFG_OFFSET … #define IN_I2S_1_CFG_OFFSET … #define IN_I2S_2_STREAM_CFG_OFFSET … #define IN_I2S_2_CFG_OFFSET … /* AUD_FMM_IOP_MISC_xxx regs */ #define IOP_SW_INIT_LOGIC … /* End register offset defines */ /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_0_REG */ #define I2S_OUT_MCLKRATE_SHIFT … /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_REG */ #define I2S_OUT_PLLCLKSEL_SHIFT … /* AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG */ #define I2S_OUT_STREAM_ENA … #define I2S_OUT_STREAM_CFG_GROUP_ID … #define I2S_OUT_STREAM_CFG_CHANNEL_GROUPING … /* AUD_FMM_IOP_IN_I2S_x_CAP */ #define I2S_IN_STREAM_CFG_CAP_ENA … #define I2S_IN_STREAM_CFG_0_GROUP_ID … /* AUD_FMM_IOP_OUT_I2S_x_I2S_CFG_REG */ #define I2S_OUT_CFGX_CLK_ENA … #define I2S_OUT_CFGX_DATA_ENABLE … #define I2S_OUT_CFGX_DATA_ALIGNMENT … #define I2S_OUT_CFGX_BITS_PER_SLOT … #define I2S_OUT_CFGX_VALID_SLOT … #define I2S_OUT_CFGX_FSYNC_WIDTH … #define I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32 … #define I2S_OUT_CFGX_SLAVE_MODE … #define I2S_OUT_CFGX_TDM_MODE … /* AUD_FMM_BF_CTRL_SOURCECH_CFGx_REG */ #define BF_SRC_CFGX_SFIFO_ENA … #define BF_SRC_CFGX_BUFFER_PAIR_ENABLE … #define BF_SRC_CFGX_SAMPLE_CH_MODE … #define BF_SRC_CFGX_SFIFO_SZ_DOUBLE … #define BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY … #define BF_SRC_CFGX_BIT_RES … #define BF_SRC_CFGX_PROCESS_SEQ_ID_VALID … /* AUD_FMM_BF_CTRL_DESTCH_CFGx_REG */ #define BF_DST_CFGX_CAP_ENA … #define BF_DST_CFGX_BUFFER_PAIR_ENABLE … #define BF_DST_CFGX_DFIFO_SZ_DOUBLE … #define BF_DST_CFGX_NOT_PAUSE_WHEN_FULL … #define BF_DST_CFGX_FCI_ID … #define BF_DST_CFGX_CAP_MODE … #define BF_DST_CFGX_PROC_SEQ_ID_VALID … /* AUD_FMM_IOP_OUT_SPDIF_xxx */ #define SPDIF_0_OUT_DITHER_ENA … #define SPDIF_0_OUT_STREAM_ENA … /* AUD_FMM_IOP_PLL_0_USER */ #define IOP_PLL_0_USER_NDIV_FRAC … /* AUD_FMM_IOP_PLL_0_ACTIVE */ #define IOP_PLL_0_ACTIVE_NDIV_FRAC … #define INIT_SSP_REGS(num) … struct pll_macro_entry { … }; /* * PLL has 3 output channels (1x, 2x, and 4x). Below are * the common MCLK frequencies used by audio driver */ static const struct pll_macro_entry pll_predef_mclk[] = …; #define CYGNUS_RATE_MIN … #define CYGNUS_RATE_MAX … /* List of valid frame sizes for tdm mode */ static const int ssp_valid_tdm_framesize[] = …; static const unsigned int cygnus_rates[] = …; static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = …; static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai) { … } static int audio_ssp_init_portregs(struct cygnus_aio_port *aio) { … } static void audio_ssp_in_enable(struct cygnus_aio_port *aio) { … } static void audio_ssp_in_disable(struct cygnus_aio_port *aio) { … } static int audio_ssp_out_enable(struct cygnus_aio_port *aio) { … } static int audio_ssp_out_disable(struct cygnus_aio_port *aio) { … } static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk, struct cygnus_aio_port *aio) { … } static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio) { … } static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } /* * This function sets the mclk frequency for pll clock */ static int cygnus_ssp_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) { … } static int cygnus_ssp_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void cygnus_ssp_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } /* * Bit Update Notes * 31 Yes TDM Mode (1 = TDM, 0 = i2s) * 30 Yes Slave Mode (1 = Slave, 0 = Master) * 29:26 No Sclks per frame * 25:18 Yes FS Width * 17:14 No Valid Slots * 13 No Bits (1 = 16 bits, 0 = 32 bits) * 12:08 No Bits per samp * 07 Yes Justifcation (1 = LSB, 0 = MSB) * 06 Yes Alignment (1 = Delay 1 clk, 0 = no delay * 05 Yes SCLK polarity (1 = Rising, 0 = Falling) * 04 Yes LRCLK Polarity (1 = High for left, 0 = Low for left) * 03:02 Yes Reserved - write as zero * 01 No Data Enable * 00 No CLK Enable */ #define I2S_OUT_CFG_REG_UPDATE_MASK … /* Input cfg is same as output, but the FS width is not a valid field */ #define I2S_IN_CFG_REG_UPDATE_MASK … int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, int len) { … } EXPORT_SYMBOL_GPL(…); static int cygnus_ssp_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { … } static int cygnus_ssp_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static int cygnus_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) { … } #ifdef CONFIG_PM_SLEEP static int __cygnus_ssp_suspend(struct snd_soc_dai *cpu_dai) { … } static int cygnus_ssp_suspend(struct snd_soc_component *component) { … } static int __cygnus_ssp_resume(struct snd_soc_dai *cpu_dai) { … } static int cygnus_ssp_resume(struct snd_soc_component *component) { … } #else #define cygnus_ssp_suspend … #define cygnus_ssp_resume … #endif static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = …; static const struct snd_soc_dai_ops cygnus_spdif_dai_ops = …; #define INIT_CPU_DAI(num) … static const struct snd_soc_dai_driver cygnus_ssp_dai_info[] = …; static const struct snd_soc_dai_driver cygnus_spdif_dai_info = …; static struct snd_soc_dai_driver cygnus_ssp_dai[CYGNUS_MAX_PORTS]; static const struct snd_soc_component_driver cygnus_ssp_component = …; /* * Return < 0 if error * Return 0 if disabled * Return 1 if enabled and node is parsed successfully */ static int parse_ssp_child_node(struct platform_device *pdev, struct device_node *dn, struct cygnus_audio *cygaud, struct snd_soc_dai_driver *p_dai) { … } static int audio_clk_init(struct platform_device *pdev, struct cygnus_audio *cygaud) { … } static int cygnus_ssp_probe(struct platform_device *pdev) { … } static void cygnus_ssp_remove(struct platform_device *pdev) { … } static const struct of_device_id cygnus_ssp_of_match[] = …; MODULE_DEVICE_TABLE(of, cygnus_ssp_of_match); static struct platform_driver cygnus_ssp_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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