// SPDX-License-Identifier: GPL-2.0 /* * RZ/G3S CPG driver * * Copyright (C) 2023 Renesas Electronics Corp. */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <dt-bindings/clock/r9a08g045-cpg.h> #include "rzg2l-cpg.h" /* RZ/G3S Specific registers. */ #define G3S_CPG_PL2_DDIV … #define G3S_CPG_SDHI_DDIV … #define G3S_CPG_PLL_DSEL … #define G3S_CPG_SDHI_DSEL … #define G3S_CLKDIVSTATUS … #define G3S_CLKSELSTATUS … /* RZ/G3S Specific division configuration. */ #define G3S_DIVPL2B … #define G3S_DIV_SDHI0 … #define G3S_DIV_SDHI1 … #define G3S_DIV_SDHI2 … /* RZ/G3S Clock status configuration. */ #define G3S_DIVPL1A_STS … #define G3S_DIVPL2B_STS … #define G3S_DIVPL3A_STS … #define G3S_DIVPL3B_STS … #define G3S_DIVPL3C_STS … #define G3S_DIV_SDHI0_STS … #define G3S_DIV_SDHI1_STS … #define G3S_DIV_SDHI2_STS … #define G3S_SEL_PLL4_STS … #define G3S_SEL_SDHI0_STS … #define G3S_SEL_SDHI1_STS … #define G3S_SEL_SDHI2_STS … /* RZ/G3S Specific clocks select. */ #define G3S_SEL_PLL4 … #define G3S_SEL_SDHI0 … #define G3S_SEL_SDHI1 … #define G3S_SEL_SDHI2 … /* PLL 1/4/6 configuration registers macro. */ #define G3S_PLL146_CONF(clk1, clk2) … #define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) … enum clk_ids { … }; /* Divider tables */ static const struct clk_div_table dtable_1_2[] = …; static const struct clk_div_table dtable_1_8[] = …; static const struct clk_div_table dtable_1_32[] = …; /* Mux clock names tables. */ static const char * const sel_sdhi[] = …; static const char * const sel_pll4[] = …; /* Mux clock indices tables. */ static const u32 mtable_sd[] = …; static const u32 mtable_pll4[] = …; static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = …; static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = …; static const struct rzg2l_reset r9a08g045_resets[] = …; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = …; static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = …; const struct rzg2l_cpg_info r9a08g045_cpg_info = …;
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