// SPDX-License-Identifier: GPL-2.0 /* * RZ/G2L Clock Pulse Generator * * Copyright (C) 2021 Renesas Electronics Corp. * * Based on renesas-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2013 Ideas On Board SPRL * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/renesas.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/reset-controller.h> #include <linux/slab.h> #include <linux/units.h> #include <dt-bindings/clock/renesas-cpg-mssr.h> #include "rzg2l-cpg.h" #ifdef DEBUG #define WARN_DEBUG … #else #define WARN_DEBUG(x) … #endif #define GET_SHIFT(val) … #define GET_WIDTH(val) … #define KDIV(val) … #define MDIV(val) … #define PDIV(val) … #define SDIV(val) … #define RZG3S_DIV_P … #define RZG3S_DIV_M … #define RZG3S_DIV_NI … #define RZG3S_DIV_NF … #define CLK_ON_R(reg) … #define CLK_MON_R(reg) … #define CLK_RST_R(reg) … #define CLK_MRST_R(reg) … #define GET_REG_OFFSET(val) … #define GET_REG_SAMPLL_CLK1(val) … #define GET_REG_SAMPLL_CLK2(val) … #define CPG_WEN_BIT … #define MAX_VCLK_FREQ … /** * struct clk_hw_data - clock hardware data * @hw: clock hw * @conf: clock configuration (register offset, shift, width) * @sconf: clock status configuration (register offset, shift, width) * @priv: CPG private data structure */ struct clk_hw_data { … }; #define to_clk_hw_data(_hw) … /** * struct sd_mux_hw_data - SD MUX clock hardware data * @hw_data: clock hw data * @mtable: clock mux table */ struct sd_mux_hw_data { … }; #define to_sd_mux_hw_data(_hw) … /** * struct div_hw_data - divider clock hardware data * @hw_data: clock hw data * @dtable: pointer to divider table * @invalid_rate: invalid rate for divider * @max_rate: maximum rate for divider * @width: divider width */ struct div_hw_data { … }; #define to_div_hw_data(_hw) … struct rzg2l_pll5_param { … }; struct rzg2l_pll5_mux_dsi_div_param { … }; /** * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data * * @rcdev: Reset controller entity * @dev: CPG device * @base: CPG register block base address * @rmw_lock: protects register accesses * @clks: Array containing all Core and Module Clocks * @num_core_clks: Number of Core Clocks in clks[] * @num_mod_clks: Number of Module Clocks in clks[] * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { … }; static void rzg2l_cpg_del_clk_provider(void *data) { … } /* Must be called in atomic context. */ static int rzg2l_cpg_wait_clk_update_done(void __iomem *base, u32 conf) { … } int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data) { … } int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data) { … } static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv) { … } static unsigned long rzg3s_div_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int rzg3s_div_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int rzg3s_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops rzg3s_div_clk_ops = …; static struct clk * __init rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, struct rzg2l_cpg_priv *priv) { … } static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, struct rzg2l_cpg_priv *priv) { … } static struct clk * __init rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { … } static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { … } static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) { … } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = …; static struct clk * __init rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { … } static unsigned long rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, unsigned long rate) { … } struct dsi_div_hw_data { … }; #define to_dsi_div_hw_data(_hw) … static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long rzg2l_cpg_get_vclk_parent_rate(struct clk_hw *hw, unsigned long rate) { … } static int rzg2l_cpg_dsi_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops rzg2l_cpg_dsi_div_ops = …; static struct clk * __init rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, struct rzg2l_cpg_priv *priv) { … } struct pll5_mux_hw_data { … }; #define to_pll5_mux_hw_data(_hw) … static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index) { … } static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw) { … } static const struct clk_ops rzg2l_cpg_pll5_4_clk_mux_ops = …; static struct clk * __init rzg2l_cpg_pll5_4_mux_clk_register(const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv) { … } struct sipll5 { … }; #define to_sipll5(_hw) … static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw, unsigned long rate) { … } static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops rzg2l_cpg_sipll5_ops = …; static struct clk * __init rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, struct clk **clks, struct rzg2l_cpg_priv *priv) { … } struct pll_clk { … }; #define to_pll(_hw) … static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops rzg2l_cpg_pll_ops = …; static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops rzg3s_cpg_pll_ops = …; static struct clk * __init rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, struct rzg2l_cpg_priv *priv, const struct clk_ops *ops) { … } static struct clk *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) { … } static void __init rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, const struct rzg2l_cpg_info *info, struct rzg2l_cpg_priv *priv) { … } /** * struct mstp_clock - MSTP gating clock * * @hw: handle between common and hardware-specific interfaces * @off: register offset * @bit: ON/MON bit * @enabled: soft state of the clock, if it is coupled with another clock * @priv: CPG/MSTP private data * @sibling: pointer to the other coupled clock */ struct mstp_clock { … }; #define to_mod_clock(_hw) … static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) { … } static int rzg2l_mod_clock_enable(struct clk_hw *hw) { … } static void rzg2l_mod_clock_disable(struct clk_hw *hw) { … } static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops rzg2l_mod_clock_ops = …; static struct mstp_clock *rzg2l_mod_clock_get_sibling(struct mstp_clock *clock, struct rzg2l_cpg_priv *priv) { … } static void __init rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, const struct rzg2l_cpg_info *info, struct rzg2l_cpg_priv *priv) { … } #define rcdev_to_priv(x) … static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops rzg2l_cpg_reset_ops = …; static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { … } static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) { … } static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, const struct of_phandle_args *clkspec) { … } /** * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure * @onecell_data: cell data * @domains: generic PM domains */ struct rzg2l_cpg_pm_domains { … }; /** * struct rzg2l_cpg_pd - RZ/G2L power domain data structure * @genpd: generic PM domain * @priv: pointer to CPG private data structure * @conf: CPG PM domain configuration info * @id: RZ/G2L power domain ID */ struct rzg2l_cpg_pd { … }; static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { … } static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev) { … } static void rzg2l_cpg_genpd_remove(void *data) { … } static void rzg2l_cpg_genpd_remove_simple(void *data) { … } static int rzg2l_cpg_power_on(struct generic_pm_domain *domain) { … } static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) { … } static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) { … } static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) { … } static struct generic_pm_domain * rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data) { … } static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) { … } static int __init rzg2l_cpg_probe(struct platform_device *pdev) { … } static const struct of_device_id rzg2l_cpg_match[] = …; static struct platform_driver rzg2l_cpg_driver = …; static int __init rzg2l_cpg_init(void) { … } subsys_initcall(rzg2l_cpg_init); MODULE_DESCRIPTION(…) …;
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