/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2012-2013 Freescale Semiconductor, Inc. */ #ifndef __FSL_SAI_H #define __FSL_SAI_H #include <linux/dma/imx-dma.h> #include <sound/dmaengine_pcm.h> #define FSL_SAI_FORMATS … /* SAI Register Map Register */ #define FSL_SAI_VERID … #define FSL_SAI_PARAM … #define FSL_SAI_TCSR(ofs) … #define FSL_SAI_TCR1(ofs) … #define FSL_SAI_TCR2(ofs) … #define FSL_SAI_TCR3(ofs) … #define FSL_SAI_TCR4(ofs) … #define FSL_SAI_TCR5(ofs) … #define FSL_SAI_TDR0 … #define FSL_SAI_TDR1 … #define FSL_SAI_TDR2 … #define FSL_SAI_TDR3 … #define FSL_SAI_TDR4 … #define FSL_SAI_TDR5 … #define FSL_SAI_TDR6 … #define FSL_SAI_TDR7 … #define FSL_SAI_TFR0 … #define FSL_SAI_TFR1 … #define FSL_SAI_TFR2 … #define FSL_SAI_TFR3 … #define FSL_SAI_TFR4 … #define FSL_SAI_TFR5 … #define FSL_SAI_TFR6 … #define FSL_SAI_TFR7 … #define FSL_SAI_TMR … #define FSL_SAI_TTCTL … #define FSL_SAI_TTCTN … #define FSL_SAI_TBCTN … #define FSL_SAI_TTCAP … #define FSL_SAI_RCSR(ofs) … #define FSL_SAI_RCR1(ofs) … #define FSL_SAI_RCR2(ofs) … #define FSL_SAI_RCR3(ofs) … #define FSL_SAI_RCR4(ofs) … #define FSL_SAI_RCR5(ofs) … #define FSL_SAI_RDR0 … #define FSL_SAI_RDR1 … #define FSL_SAI_RDR2 … #define FSL_SAI_RDR3 … #define FSL_SAI_RDR4 … #define FSL_SAI_RDR5 … #define FSL_SAI_RDR6 … #define FSL_SAI_RDR7 … #define FSL_SAI_RFR0 … #define FSL_SAI_RFR1 … #define FSL_SAI_RFR2 … #define FSL_SAI_RFR3 … #define FSL_SAI_RFR4 … #define FSL_SAI_RFR5 … #define FSL_SAI_RFR6 … #define FSL_SAI_RFR7 … #define FSL_SAI_RMR … #define FSL_SAI_RTCTL … #define FSL_SAI_RTCTN … #define FSL_SAI_RBCTN … #define FSL_SAI_RTCAP … #define FSL_SAI_MCTL … #define FSL_SAI_MDIV … #define FSL_SAI_xCSR(tx, ofs) … #define FSL_SAI_xCR1(tx, ofs) … #define FSL_SAI_xCR2(tx, ofs) … #define FSL_SAI_xCR3(tx, ofs) … #define FSL_SAI_xCR4(tx, ofs) … #define FSL_SAI_xCR5(tx, ofs) … #define FSL_SAI_xDR0(tx) … #define FSL_SAI_xFR0(tx) … #define FSL_SAI_xMR(tx) … /* SAI Transmit/Receive Control Register */ #define FSL_SAI_CSR_TERE … #define FSL_SAI_CSR_SE … #define FSL_SAI_CSR_BCE … #define FSL_SAI_CSR_FR … #define FSL_SAI_CSR_SR … #define FSL_SAI_CSR_xF_SHIFT … #define FSL_SAI_CSR_xF_W_SHIFT … #define FSL_SAI_CSR_xF_MASK … #define FSL_SAI_CSR_xF_W_MASK … #define FSL_SAI_CSR_WSF … #define FSL_SAI_CSR_SEF … #define FSL_SAI_CSR_FEF … #define FSL_SAI_CSR_FWF … #define FSL_SAI_CSR_FRF … #define FSL_SAI_CSR_xIE_SHIFT … #define FSL_SAI_CSR_xIE_MASK … #define FSL_SAI_CSR_WSIE … #define FSL_SAI_CSR_SEIE … #define FSL_SAI_CSR_FEIE … #define FSL_SAI_CSR_FWIE … #define FSL_SAI_CSR_FRIE … #define FSL_SAI_CSR_FRDE … /* SAI Transmit and Receive Configuration 1 Register */ #define FSL_SAI_CR1_RFW_MASK(x) … /* SAI Transmit and Receive Configuration 2 Register */ #define FSL_SAI_CR2_SYNC … #define FSL_SAI_CR2_BCI … #define FSL_SAI_CR2_MSEL_MASK … #define FSL_SAI_CR2_MSEL_BUS … #define FSL_SAI_CR2_MSEL_MCLK1 … #define FSL_SAI_CR2_MSEL_MCLK2 … #define FSL_SAI_CR2_MSEL_MCLK3 … #define FSL_SAI_CR2_MSEL(ID) … #define FSL_SAI_CR2_BCP … #define FSL_SAI_CR2_BCD_MSTR … #define FSL_SAI_CR2_BYP … #define FSL_SAI_CR2_DIV_MASK … /* SAI Transmit and Receive Configuration 3 Register */ #define FSL_SAI_CR3_TRCE(x) … #define FSL_SAI_CR3_TRCE_MASK … #define FSL_SAI_CR3_WDFL(x) … #define FSL_SAI_CR3_WDFL_MASK … /* SAI Transmit and Receive Configuration 4 Register */ #define FSL_SAI_CR4_FCONT … #define FSL_SAI_CR4_FCOMB_SHIFT … #define FSL_SAI_CR4_FCOMB_SOFT … #define FSL_SAI_CR4_FCOMB_MASK … #define FSL_SAI_CR4_FPACK_8 … #define FSL_SAI_CR4_FPACK_16 … #define FSL_SAI_CR4_FRSZ(x) … #define FSL_SAI_CR4_FRSZ_MASK … #define FSL_SAI_CR4_SYWD(x) … #define FSL_SAI_CR4_SYWD_MASK … #define FSL_SAI_CR4_CHMOD … #define FSL_SAI_CR4_CHMOD_MASK … #define FSL_SAI_CR4_MF … #define FSL_SAI_CR4_FSE … #define FSL_SAI_CR4_FSP … #define FSL_SAI_CR4_FSD_MSTR … /* SAI Transmit and Receive Configuration 5 Register */ #define FSL_SAI_CR5_WNW(x) … #define FSL_SAI_CR5_WNW_MASK … #define FSL_SAI_CR5_W0W(x) … #define FSL_SAI_CR5_W0W_MASK … #define FSL_SAI_CR5_FBT(x) … #define FSL_SAI_CR5_FBT_MASK … /* SAI MCLK Control Register */ #define FSL_SAI_MCTL_MCLK_EN … #define FSL_SAI_MCTL_MSEL_MASK … #define FSL_SAI_MCTL_MSEL(ID) … #define FSL_SAI_MCTL_MSEL_BUS … #define FSL_SAI_MCTL_MSEL_MCLK1 … #define FSL_SAI_MCTL_MSEL_MCLK2 … #define FSL_SAI_MCTL_MSEL_MCLK3 … #define FSL_SAI_MCTL_DIV_EN … #define FSL_SAI_MCTL_DIV_MASK … /* SAI VERID Register */ #define FSL_SAI_VERID_MAJOR_SHIFT … #define FSL_SAI_VERID_MAJOR_MASK … #define FSL_SAI_VERID_MINOR_SHIFT … #define FSL_SAI_VERID_MINOR_MASK … #define FSL_SAI_VERID_FEATURE_SHIFT … #define FSL_SAI_VERID_FEATURE_MASK … #define FSL_SAI_VERID_EFIFO_EN … #define FSL_SAI_VERID_TSTMP_EN … /* SAI PARAM Register */ #define FSL_SAI_PARAM_SPF_SHIFT … #define FSL_SAI_PARAM_SPF_MASK … #define FSL_SAI_PARAM_WPF_SHIFT … #define FSL_SAI_PARAM_WPF_MASK … #define FSL_SAI_PARAM_DLN_MASK … /* SAI MCLK Divide Register */ #define FSL_SAI_MDIV_MASK … /* SAI timestamp and bitcounter */ #define FSL_SAI_xTCTL_TSEN … #define FSL_SAI_xTCTL_TSINC … #define FSL_SAI_xTCTL_RTSC … #define FSL_SAI_xTCTL_RBC … /* SAI type */ #define FSL_SAI_DMA … #define FSL_SAI_USE_AC97 … #define FSL_SAI_NET … #define FSL_SAI_TRA_SYN … #define FSL_SAI_REC_SYN … #define FSL_SAI_USE_I2S_SLAVE … /* SAI clock sources */ #define FSL_SAI_CLK_BUS … #define FSL_SAI_CLK_MAST1 … #define FSL_SAI_CLK_MAST2 … #define FSL_SAI_CLK_MAST3 … #define FSL_SAI_MCLK_MAX … /* SAI data transfer numbers per DMA request */ #define FSL_SAI_MAXBURST_TX … #define FSL_SAI_MAXBURST_RX … #define PMQOS_CPU_LATENCY … /* Max number of dataline */ #define FSL_SAI_DL_NUM … /* default dataline type is zero */ #define FSL_SAI_DL_DEFAULT … #define FSL_SAI_DL_I2S … #define FSL_SAI_DL_PDM … struct fsl_sai_soc_data { … }; /** * struct fsl_sai_verid - version id data * @version: version number * @feature: feature specification number * 0000000000000000b - Standard feature set * 0000000000000000b - Standard feature set */ struct fsl_sai_verid { … }; /** * struct fsl_sai_param - parameter data * @slot_num: The maximum number of slots per frame * @fifo_depth: The number of words in each FIFO (depth) * @dataline: The number of datalines implemented */ struct fsl_sai_param { … }; struct fsl_sai_dl_cfg { … }; struct fsl_sai { … }; #define TX … #define RX … #endif /* __FSL_SAI_H */
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