/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * PDM Microphone Interface for the NXP i.MX SoC * Copyright 2018 NXP */ #ifndef _FSL_MICFIL_H #define _FSL_MICFIL_H /* MICFIL Register Map */ #define REG_MICFIL_CTRL1 … #define REG_MICFIL_CTRL2 … #define REG_MICFIL_STAT … #define REG_MICFIL_FIFO_CTRL … #define REG_MICFIL_FIFO_STAT … #define REG_MICFIL_DATACH0 … #define REG_MICFIL_DATACH1 … #define REG_MICFIL_DATACH2 … #define REG_MICFIL_DATACH3 … #define REG_MICFIL_DATACH4 … #define REG_MICFIL_DATACH5 … #define REG_MICFIL_DATACH6 … #define REG_MICFIL_DATACH7 … #define REG_MICFIL_DC_CTRL … #define REG_MICFIL_OUT_CTRL … #define REG_MICFIL_OUT_STAT … #define REG_MICFIL_FSYNC_CTRL … #define REG_MICFIL_VERID … #define REG_MICFIL_PARAM … #define REG_MICFIL_VAD0_CTRL1 … #define REG_MICFIL_VAD0_CTRL2 … #define REG_MICFIL_VAD0_STAT … #define REG_MICFIL_VAD0_SCONFIG … #define REG_MICFIL_VAD0_NCONFIG … #define REG_MICFIL_VAD0_NDATA … #define REG_MICFIL_VAD0_ZCD … /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ #define MICFIL_CTRL1_MDIS … #define MICFIL_CTRL1_DOZEN … #define MICFIL_CTRL1_PDMIEN … #define MICFIL_CTRL1_DBG … #define MICFIL_CTRL1_SRES … #define MICFIL_CTRL1_DBGE … #define MICFIL_CTRL1_DECFILS … #define MICFIL_CTRL1_FSYNCEN … #define MICFIL_CTRL1_DISEL_DISABLE … #define MICFIL_CTRL1_DISEL_DMA … #define MICFIL_CTRL1_DISEL_IRQ … #define MICFIL_CTRL1_DISEL … #define MICFIL_CTRL1_ERREN … #define MICFIL_CTRL1_CHEN(ch) … /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ #define MICFIL_CTRL2_QSEL_SHIFT … #define MICFIL_CTRL2_QSEL … #define MICFIL_QSEL_MEDIUM_QUALITY … #define MICFIL_QSEL_HIGH_QUALITY … #define MICFIL_QSEL_LOW_QUALITY … #define MICFIL_QSEL_VLOW0_QUALITY … #define MICFIL_QSEL_VLOW1_QUALITY … #define MICFIL_QSEL_VLOW2_QUALITY … #define MICFIL_CTRL2_CICOSR … #define MICFIL_CTRL2_CLKDIV … /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ #define MICFIL_STAT_BSY_FIL … #define MICFIL_STAT_FIR_RDY … #define MICFIL_STAT_LOWFREQF … #define MICFIL_STAT_CHXF(ch) … /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ #define MICFIL_FIFO_CTRL_FIFOWMK … /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) … #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) … /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */ #define MICFIL_DC_CTRL_CONFIG … #define MICFIL_DC_CHX_SHIFT(ch) … #define MICFIL_DC_CHX(ch) … #define MICFIL_DC_CUTOFF_21HZ … #define MICFIL_DC_CUTOFF_83HZ … #define MICFIL_DC_CUTOFF_152Hz … #define MICFIL_DC_BYPASS … /* MICFIL VERID Register -- REG_MICFIL_VERID */ #define MICFIL_VERID_MAJOR_SHIFT … #define MICFIL_VERID_MAJOR_MASK … #define MICFIL_VERID_MINOR_SHIFT … #define MICFIL_VERID_MINOR_MASK … #define MICFIL_VERID_FEATURE_SHIFT … #define MICFIL_VERID_FEATURE_MASK … /* MICFIL PARAM Register -- REG_MICFIL_PARAM */ #define MICFIL_PARAM_NUM_HWVAD_SHIFT … #define MICFIL_PARAM_NUM_HWVAD_MASK … #define MICFIL_PARAM_HWVAD_ZCD … #define MICFIL_PARAM_HWVAD_ENERGY_MODE … #define MICFIL_PARAM_HWVAD … #define MICFIL_PARAM_DC_OUT_BYPASS … #define MICFIL_PARAM_DC_IN_BYPASS … #define MICFIL_PARAM_LOW_POWER … #define MICFIL_PARAM_FIL_OUT_WIDTH … #define MICFIL_PARAM_FIFO_PTRWID_SHIFT … #define MICFIL_PARAM_FIFO_PTRWID_MASK … #define MICFIL_PARAM_NPAIR_SHIFT … #define MICFIL_PARAM_NPAIR_MASK … /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ #define MICFIL_VAD0_CTRL1_CHSEL … #define MICFIL_VAD0_CTRL1_CICOSR … #define MICFIL_VAD0_CTRL1_INITT … #define MICFIL_VAD0_CTRL1_ST10 … #define MICFIL_VAD0_CTRL1_ERIE … #define MICFIL_VAD0_CTRL1_IE … #define MICFIL_VAD0_CTRL1_RST … #define MICFIL_VAD0_CTRL1_EN … /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ #define MICFIL_VAD0_CTRL2_FRENDIS … #define MICFIL_VAD0_CTRL2_PREFEN … #define MICFIL_VAD0_CTRL2_FOUTDIS … #define MICFIL_VAD0_CTRL2_FRAMET … #define MICFIL_VAD0_CTRL2_INPGAIN … #define MICFIL_VAD0_CTRL2_HPF … /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ #define MICFIL_VAD0_SCONFIG_SFILEN … #define MICFIL_VAD0_SCONFIG_SMAXEN … #define MICFIL_VAD0_SCONFIG_SGAIN … /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ #define MICFIL_VAD0_NCONFIG_NFILAUT … #define MICFIL_VAD0_NCONFIG_NMINEN … #define MICFIL_VAD0_NCONFIG_NDECEN … #define MICFIL_VAD0_NCONFIG_NOREN … #define MICFIL_VAD0_NCONFIG_NFILADJ … #define MICFIL_VAD0_NCONFIG_NGAIN … /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ #define MICFIL_VAD0_ZCD_ZCDTH … #define MICFIL_VAD0_ZCD_ZCDADJ … #define MICFIL_VAD0_ZCD_ZCDAND … #define MICFIL_VAD0_ZCD_ZCDAUT … #define MICFIL_VAD0_ZCD_ZCDEN … /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ #define MICFIL_VAD0_STAT_INITF … #define MICFIL_VAD0_STAT_INSATF … #define MICFIL_VAD0_STAT_EF … #define MICFIL_VAD0_STAT_IF … /* MICFIL Output Control Register */ #define MICFIL_OUTGAIN_CHX_SHIFT(v) … /* Constants */ #define MICFIL_OUTPUT_CHANNELS … #define MICFIL_FIFO_NUM … #define FIFO_PTRWID … #define FIFO_LEN … #define MICFIL_IRQ_LINES … #define MICFIL_MAX_RETRY … #define MICFIL_SLEEP_MIN … #define MICFIL_SLEEP_MAX … #define MICFIL_DMA_MAXBURST_RX … /* HWVAD Constants */ #define MICFIL_HWVAD_ENVELOPE_MODE … #define MICFIL_HWVAD_ENERGY_MODE … /** * struct fsl_micfil_verid - version id data * @version: version number * @feature: feature specification number */ struct fsl_micfil_verid { … }; /** * struct fsl_micfil_param - parameter data * @hwvad_num: the number of HWVADs * @hwvad_zcd: HWVAD zero-cross detector is active * @hwvad_energy_mode: HWVAD energy mode is active * @hwvad: HWVAD is active * @dc_out_bypass: points out if the output DC remover is disabled * @dc_in_bypass: points out if the input DC remover is disabled * @low_power: low power decimation filter * @fil_out_width: filter output width * @fifo_ptrwid: FIFO pointer width * @npair: number of microphone pairs */ struct fsl_micfil_param { … }; #endif /* _FSL_MICFIL_H */
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