/* SPDX-License-Identifier: GPL-2.0 */ /* * NXP XCVR ALSA SoC Digital Audio Interface (DAI) driver * * Copyright 2019 NXP */ #ifndef __FSL_XCVR_H #define __FSL_XCVR_H #define FSL_XCVR_MODE_SPDIF … #define FSL_XCVR_MODE_ARC … #define FSL_XCVR_MODE_EARC … /* XCVR Registers */ #define FSL_XCVR_REG_OFFSET … #define FSL_XCVR_FIFO_SIZE … #define FSL_XCVR_FIFO_WMK_RX … #define FSL_XCVR_FIFO_WMK_TX … #define FSL_XCVR_MAXBURST_RX … #define FSL_XCVR_MAXBURST_TX … #define FSL_XCVR_RX_FIFO_ADDR … #define FSL_XCVR_TX_FIFO_ADDR … #define FSL_XCVR_VERSION … #define FSL_XCVR_EXT_CTRL … #define FSL_XCVR_EXT_STATUS … #define FSL_XCVR_EXT_IER0 … #define FSL_XCVR_EXT_IER1 … #define FSL_XCVR_EXT_ISR … #define FSL_XCVR_EXT_ISR_SET … #define FSL_XCVR_EXT_ISR_CLR … #define FSL_XCVR_EXT_ISR_TOG … #define FSL_XCVR_IER … #define FSL_XCVR_ISR … #define FSL_XCVR_ISR_SET … #define FSL_XCVR_ISR_CLR … #define FSL_XCVR_ISR_TOG … #define FSL_XCVR_PHY_AI_CTRL … #define FSL_XCVR_PHY_AI_CTRL_SET … #define FSL_XCVR_PHY_AI_CTRL_CLR … #define FSL_XCVR_PHY_AI_CTRL_TOG … #define FSL_XCVR_PHY_AI_WDATA … #define FSL_XCVR_PHY_AI_RDATA … #define FSL_XCVR_CLK_CTRL … #define FSL_XCVR_RX_DPTH_CTRL … #define FSL_XCVR_RX_DPTH_CTRL_SET … #define FSL_XCVR_RX_DPTH_CTRL_CLR … #define FSL_XCVR_RX_DPTH_CTRL_TOG … #define FSL_XCVR_RX_CS_DATA_0 … #define FSL_XCVR_RX_CS_DATA_1 … #define FSL_XCVR_RX_CS_DATA_2 … #define FSL_XCVR_RX_CS_DATA_3 … #define FSL_XCVR_RX_CS_DATA_4 … #define FSL_XCVR_RX_CS_DATA_5 … #define FSL_XCVR_RX_DPTH_CNTR_CTRL … #define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET … #define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR … #define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG … #define FSL_XCVR_RX_DPTH_TSCR … #define FSL_XCVR_RX_DPTH_BCR … #define FSL_XCVR_RX_DPTH_BCTR … #define FSL_XCVR_RX_DPTH_BCRR … #define FSL_XCVR_TX_DPTH_CTRL … #define FSL_XCVR_TX_DPTH_CTRL_SET … #define FSL_XCVR_TX_DPTH_CTRL_CLR … #define FSL_XCVR_TX_DPTH_CTRL_TOG … #define FSL_XCVR_TX_CS_DATA_0 … #define FSL_XCVR_TX_CS_DATA_1 … #define FSL_XCVR_TX_CS_DATA_2 … #define FSL_XCVR_TX_CS_DATA_3 … #define FSL_XCVR_TX_CS_DATA_4 … #define FSL_XCVR_TX_CS_DATA_5 … #define FSL_XCVR_TX_DPTH_CNTR_CTRL … #define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET … #define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR … #define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG … #define FSL_XCVR_TX_DPTH_TSCR … #define FSL_XCVR_TX_DPTH_BCR … #define FSL_XCVR_TX_DPTH_BCTR … #define FSL_XCVR_TX_DPTH_BCRR … #define FSL_XCVR_DEBUG_REG_0 … #define FSL_XCVR_DEBUG_REG_1 … #define FSL_XCVR_MAX_REG … #define FSL_XCVR_EXT_CTRL_CORE_RESET … #define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET … #define FSL_XCVR_EXT_CTRL_TX_CMDC_RESET … #define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) … #define FSL_XCVR_EXT_CTRL_RX_DPTH_RESET … #define FSL_XCVR_EXT_CTRL_TX_DPTH_RESET … #define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) … #define FSL_XCVR_EXT_CTRL_TX_RX_MODE … #define FSL_XCVR_EXT_CTRL_DMA_RD_DIS … #define FSL_XCVR_EXT_CTRL_DMA_WR_DIS … #define FSL_XCVR_EXT_CTRL_DMA_DIS(t) … #define FSL_XCVR_EXT_CTRL_SPDIF_MODE … #define FSL_XCVR_EXT_CTRL_SLEEP_MODE … #define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT … #define FSL_XCVR_EXT_CTRL_TX_FWM_MASK … #define FSL_XCVR_EXT_CTRL_TX_FWM(i) … #define FSL_XCVR_EXT_CTRL_RX_FWM_SHFT … #define FSL_XCVR_EXT_CTRL_RX_FWM_MASK … #define FSL_XCVR_EXT_CTRL_RX_FWM(i) … #define FSL_XCVR_EXT_CTRL_PAGE_SHFT … #define FSL_XCVR_EXT_CTRL_PAGE_MASK … #define FSL_XCVR_EXT_CTRL_PAGE(i) … #define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR … #define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR … #define FSL_XCVR_EXT_STUS_CM0_SLEEPING … #define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP … #define FSL_XCVR_EXT_STUS_CM0_SLP_HACK … #define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO … #define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO … #define FSL_XCVR_EXT_STUS_RX_CMDC_COTO … #define FSL_XCVR_EXT_STUS_TX_CMDC_COTO … #define FSL_XCVR_EXT_STUS_HB_STATUS … #define FSL_XCVR_EXT_STUS_NEW_UD4_REC … #define FSL_XCVR_EXT_STUS_NEW_UD5_REC … #define FSL_XCVR_EXT_STUS_NEW_UD6_REC … #define FSL_XCVR_EXT_STUS_HPD_INPUT … #define FSL_XCVR_IRQ_NEW_CS … #define FSL_XCVR_IRQ_NEW_UD … #define FSL_XCVR_IRQ_MUTE … #define FSL_XCVR_IRQ_CMDC_RESP_TO … #define FSL_XCVR_IRQ_ECC_ERR … #define FSL_XCVR_IRQ_PREAMBLE_MISMATCH … #define FSL_XCVR_IRQ_FIFO_UOFL_ERR … #define FSL_XCVR_IRQ_HOST_WAKEUP … #define FSL_XCVR_IRQ_HOST_OHPD … #define FSL_XCVR_IRQ_DMAC_NO_DATA_REC … #define FSL_XCVR_IRQ_DMAC_FMT_CHG_DET … #define FSL_XCVR_IRQ_HB_STATE_CHG … #define FSL_XCVR_IRQ_CMDC_STATUS_UPD … #define FSL_XCVR_IRQ_TEMP_UPD … #define FSL_XCVR_IRQ_DMA_RD_REQ … #define FSL_XCVR_IRQ_DMA_WR_REQ … #define FSL_XCVR_IRQ_DMAC_BME_BIT_ERR … #define FSL_XCVR_IRQ_PREAMBLE_MATCH … #define FSL_XCVR_IRQ_M_W_PRE_MISMATCH … #define FSL_XCVR_IRQ_B_PRE_MISMATCH … #define FSL_XCVR_IRQ_UNEXP_PRE_REC … #define FSL_XCVR_IRQ_ARC_MODE … #define FSL_XCVR_IRQ_CH_UD_OFLOW … #define FSL_XCVR_IRQ_EARC_ALL … #define FSL_XCVR_ISR_CMDC_TX_EN … #define FSL_XCVR_ISR_HPD_TGL … #define FSL_XCVR_ISR_DMAC_SPARE_INT … #define FSL_XCVR_ISR_SET_SPDIF_RX_INT … #define FSL_XCVR_ISR_SET_SPDIF_TX_INT … #define FSL_XCVR_ISR_SET_SPDIF_MODE(t) … #define FSL_XCVR_ISR_SET_ARC_CM_INT … #define FSL_XCVR_ISR_SET_ARC_SE_INT … #define FSL_XCVR_PHY_AI_ADDR_MASK … #define FSL_XCVR_PHY_AI_RESETN … #define FSL_XCVR_PHY_AI_TOG_PLL … #define FSL_XCVR_PHY_AI_TOG_DONE_PLL … #define FSL_XCVR_PHY_AI_TOG_PHY … #define FSL_XCVR_PHY_AI_TOG_DONE_PHY … #define FSL_XCVR_PHY_AI_RW_MASK … #define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS … #define FSL_XCVR_RX_DPTH_CTRL_DIS_PRE_ERR_CHK … #define FSL_XCVR_RX_DPTH_CTRL_DIS_NOD_REC_CHK … #define FSL_XCVR_RX_DPTH_CTRL_ECC_VUC_BIT_CHK … #define FSL_XCVR_RX_DPTH_CTRL_EN_CMP_PAR_CALC … #define FSL_XCVR_RX_DPTH_CTRL_RST_PKT_CNT_FIFO … #define FSL_XCVR_RX_DPTH_CTRL_STORE_FMT … #define FSL_XCVR_RX_DPTH_CTRL_EN_PAR_CALC … #define FSL_XCVR_RX_DPTH_CTRL_UDR … #define FSL_XCVR_RX_DPTH_CTRL_CSR … #define FSL_XCVR_RX_DPTH_CTRL_UDA … #define FSL_XCVR_RX_DPTH_CTRL_CSA … #define FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO … #define FSL_XCVR_RX_DPTH_CTRL_DIS_B_PRE_ERR_CHK … #define FSL_XCVR_RX_DPTH_CTRL_PABS … #define FSL_XCVR_RX_DPTH_CTRL_DTS_CDS … #define FSL_XCVR_RX_DPTH_CTRL_BLKC … #define FSL_XCVR_RX_DPTH_CTRL_MUTE_CTRL … #define FSL_XCVR_RX_DPTH_CTRL_MUTE_MODE … #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_CTRL … #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE … #define FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL … #define FSL_XCVR_RX_DPTH_CTRL_LAYB_MODE … #define FSL_XCVR_RX_DPTH_CTRL_PRC … #define FSL_XCVR_RX_DPTH_CTRL_COMP … #define FSL_XCVR_RX_DPTH_CTRL_FSM … #define FSL_XCVR_TX_DPTH_CTRL_CS_ACK … #define FSL_XCVR_TX_DPTH_CTRL_UD_ACK … #define FSL_XCVR_TX_DPTH_CTRL_CS_MOD … #define FSL_XCVR_TX_DPTH_CTRL_UD_MOD … #define FSL_XCVR_TX_DPTH_CTRL_VLD_MOD … #define FSL_XCVR_TX_DPTH_CTRL_FRM_VLD … #define FSL_XCVR_TX_DPTH_CTRL_EN_PARITY … #define FSL_XCVR_TX_DPTH_CTRL_EN_PREAMBLE … #define FSL_XCVR_TX_DPTH_CTRL_EN_ECC_INTER … #define FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM … #define FSL_XCVR_TX_DPTH_CTRL_FRM_FMT … #define FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX … #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_STR … #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_END … #define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO … #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME … #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN … #define FSL_XCVR_PLL_CTRL0 … #define FSL_XCVR_PLL_CTRL0_SET … #define FSL_XCVR_PLL_CTRL0_CLR … #define FSL_XCVR_PLL_NUM … #define FSL_XCVR_PLL_DEN … #define FSL_XCVR_PLL_PDIV … #define FSL_XCVR_PLL_BANDGAP_SET … #define FSL_XCVR_PHY_CTRL … #define FSL_XCVR_PHY_CTRL_SET … #define FSL_XCVR_PHY_CTRL_CLR … #define FSL_XCVR_PHY_CTRL2 … #define FSL_XCVR_PHY_CTRL2_SET … #define FSL_XCVR_PHY_CTRL2_CLR … #define FSL_XCVR_PLL_BANDGAP_EN_VBG … #define FSL_XCVR_PLL_CTRL0_HROFF … #define FSL_XCVR_PLL_CTRL0_PWP … #define FSL_XCVR_PLL_CTRL0_CM0_EN … #define FSL_XCVR_PLL_CTRL0_CM1_EN … #define FSL_XCVR_PLL_CTRL0_CM2_EN … #define FSL_XCVR_PLL_PDIVx(v, i) … #define FSL_XCVR_PHY_CTRL_PHY_EN … #define FSL_XCVR_PHY_CTRL_RX_CM_EN … #define FSL_XCVR_PHY_CTRL_TSDIFF_OE … #define FSL_XCVR_PHY_CTRL_SPDIF_EN … #define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN … #define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN … #define FSL_XCVR_PHY_CTRL_TX_CLK_MASK … #define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS … #define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS … #define FSL_XCVR_PHY_CTRL2_EARC_TXMS … #define FSL_XCVR_CS_DATA_0_FS_MASK … #define FSL_XCVR_CS_DATA_0_FS_32000 … #define FSL_XCVR_CS_DATA_0_FS_44100 … #define FSL_XCVR_CS_DATA_0_FS_48000 … #define FSL_XCVR_CS_DATA_0_FS_64000 … #define FSL_XCVR_CS_DATA_0_FS_88200 … #define FSL_XCVR_CS_DATA_0_FS_96000 … #define FSL_XCVR_CS_DATA_0_FS_176400 … #define FSL_XCVR_CS_DATA_0_FS_192000 … #define FSL_XCVR_CS_DATA_0_CH_MASK … #define FSL_XCVR_CS_DATA_0_CH_U2LPCM … #define FSL_XCVR_CS_DATA_0_CH_UMLPCM … #define FSL_XCVR_CS_DATA_0_CH_U1BAUD … #define FSL_XCVR_CS_DATA_1_CH_MASK … #define FSL_XCVR_CS_DATA_1_CH_2 … #define FSL_XCVR_CS_DATA_1_CH_8 … #define FSL_XCVR_CS_DATA_1_CH_16 … #define FSL_XCVR_CS_DATA_1_CH_32 … /* Data memory structures */ #define FSL_XCVR_RX_CS_CTRL_0 … #define FSL_XCVR_RX_CS_CTRL_1 … #define FSL_XCVR_RX_CS_BUFF_0 … #define FSL_XCVR_RX_CS_BUFF_1 … #define FSL_XCVR_CAP_DATA_STR … /* GP PLL Registers */ #define FSL_XCVR_GP_PLL_CTRL … #define FSL_XCVR_GP_PLL_CTRL_SET … #define FSL_XCVR_GP_PLL_CTRL_CLR … #define FSL_XCVR_GP_PLL_CTRL_TOG … #define FSL_XCVR_GP_PLL_ANA_PRG … #define FSL_XCVR_GP_PLL_ANA_PRG_SET … #define FSL_XCVR_GP_PLL_ANA_PRG_CLR … #define FSL_XCVR_GP_PLL_ANA_PRG_TOG … #define FSL_XCVR_GP_PLL_TEST … #define FSL_XCVR_GP_PLL_TEST_SET … #define FSL_XCVR_GP_PLL_TEST_CLR … #define FSL_XCVR_GP_PLL_TEST_TOG … #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM … #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_SET … #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_CLR … #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_TOG … #define FSL_XCVR_GP_PLL_NUMERATOR … #define FSL_XCVR_GP_PLL_NUMERATOR_SET … #define FSL_XCVR_GP_PLL_NUMERATOR_CLR … #define FSL_XCVR_GP_PLL_NUMERATOR_TOG … #define FSL_XCVR_GP_PLL_DENOMINATOR … #define FSL_XCVR_GP_PLL_DENOMINATOR_SET … #define FSL_XCVR_GP_PLL_DENOMINATOR_CLR … #define FSL_XCVR_GP_PLL_DENOMINATOR_TOG … #define FSL_XCVR_GP_PLL_DIV … #define FSL_XCVR_GP_PLL_DIV_SET … #define FSL_XCVR_GP_PLL_DIV_CLR … #define FSL_XCVR_GP_PLL_DIV_TOG … #define FSL_XCVR_GP_PLL_DFS_CTRL0 … #define FSL_XCVR_GP_PLL_DFS_CTRL0_SET … #define FSL_XCVR_GP_PLL_DFS_CTRL0_CLR … #define FSL_XCVR_GP_PLL_DFS_CTRL0_TOG … #define FSL_XCVR_GP_PLL_DFS_DIV0 … #define FSL_XCVR_GP_PLL_DFS_DIV0_SET … #define FSL_XCVR_GP_PLL_DFS_DIV0_CLR … #define FSL_XCVR_GP_PLL_DFS_DIV0_TOG … #define FSL_XCVR_GP_PLL_DFS_CTRL1 … #define FSL_XCVR_GP_PLL_DFS_CTRL1_SET … #define FSL_XCVR_GP_PLL_DFS_CTRL1_CLR … #define FSL_XCVR_GP_PLL_DFS_CTRL1_TOG … #define FSL_XCVR_GP_PLL_DFS_DIV1 … #define FSL_XCVR_GP_PLL_DFS_DIV1_SET … #define FSL_XCVR_GP_PLL_DFS_DIV1_CLR … #define FSL_XCVR_GP_PLL_DFS_DIV1_TOG … #define FSL_XCVR_GP_PLL_DFS_CTRL2 … #define FSL_XCVR_GP_PLL_DFS_CTRL2_SET … #define FSL_XCVR_GP_PLL_DFS_CTRL2_CLR … #define FSL_XCVR_GP_PLL_DFS_CTRL2_TOG … #define FSL_XCVR_GP_PLL_DFS_DIV2 … #define FSL_XCVR_GP_PLL_DFS_DIV2_SET … #define FSL_XCVR_GP_PLL_DFS_DIV2_CLR … #define FSL_XCVR_GP_PLL_DFS_DIV2_TOG … #define FSL_XCVR_GP_PLL_DFS_CTRL3 … #define FSL_XCVR_GP_PLL_DFS_CTRL3_SET … #define FSL_XCVR_GP_PLL_DFS_CTRL3_CLR … #define FSL_XCVR_GP_PLL_DFS_CTRL3_TOG … #define FSL_XCVR_GP_PLL_DFS_DIV3 … #define FSL_XCVR_GP_PLL_DFS_DIV3_SET … #define FSL_XCVR_GP_PLL_DFS_DIV3_CLR … #define FSL_XCVR_GP_PLL_DFS_DIV3_TOG … #define FSL_XCVR_GP_PLL_STATUS … #define FSL_XCVR_GP_PLL_STATUS_SET … #define FSL_XCVR_GP_PLL_STATUS_CLR … #define FSL_XCVR_GP_PLL_STATUS_TOG … /* GP PLL Control Register */ #define FSL_XCVR_GP_PLL_CTRL_LBYPASS … #define FSL_XCVR_GP_PLL_CTRL_HCS … #define FSL_XCVR_GP_PLL_CTRL_MSD … #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN3 … #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN2 … #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN1 … #define FSL_XCVR_GP_PLL_CTRL_SPREADCTL … #define FSL_XCVR_GP_PLL_CTRL_CLKMUX_BYPASS … #define FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN … #define FSL_XCVR_GP_PLL_CTRL_POWERUP … /* GP PLL Numerator Register */ #define FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT … #define FSL_XCVR_GP_PLL_NUMERATOR_MFN … /* GP PLL Denominator Register */ #define FSL_XCVR_GP_PLL_DENOMINATOR_MFD … /* GP PLL Dividers Register */ #define FSL_XCVR_GP_PLL_DIV_MFI_SHIFT … #define FSL_XCVR_GP_PLL_DIV_MFI … #define FSL_XCVR_GP_PLL_DIV_RDIV … #define FSL_XCVR_GP_PLL_DIV_ODIV … #endif /* __FSL_XCVR_H */
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