/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019 NXP */ #ifndef _FSL_EASRC_H #define _FSL_EASRC_H #include <sound/asound.h> #include <linux/dma/imx-dma.h> #include "fsl_asrc_common.h" /* EASRC Register Map */ /* ASRC Input Write FIFO */ #define REG_EASRC_WRFIFO(ctx) … /* ASRC Output Read FIFO */ #define REG_EASRC_RDFIFO(ctx) … /* ASRC Context Control */ #define REG_EASRC_CC(ctx) … /* ASRC Context Control Extended 1 */ #define REG_EASRC_CCE1(ctx) … /* ASRC Context Control Extended 2 */ #define REG_EASRC_CCE2(ctx) … /* ASRC Control Input Access */ #define REG_EASRC_CIA(ctx) … /* ASRC Datapath Processor Control Slot0 */ #define REG_EASRC_DPCS0R0(ctx) … #define REG_EASRC_DPCS0R1(ctx) … #define REG_EASRC_DPCS0R2(ctx) … #define REG_EASRC_DPCS0R3(ctx) … /* ASRC Datapath Processor Control Slot1 */ #define REG_EASRC_DPCS1R0(ctx) … #define REG_EASRC_DPCS1R1(ctx) … #define REG_EASRC_DPCS1R2(ctx) … #define REG_EASRC_DPCS1R3(ctx) … /* ASRC Context Output Control */ #define REG_EASRC_COC(ctx) … /* ASRC Control Output Access */ #define REG_EASRC_COA(ctx) … /* ASRC Sample FIFO Status */ #define REG_EASRC_SFS(ctx) … /* ASRC Resampling Ratio Low */ #define REG_EASRC_RRL(ctx) … /* ASRC Resampling Ratio High */ #define REG_EASRC_RRH(ctx) … /* ASRC Resampling Ratio Update Control */ #define REG_EASRC_RUC(ctx) … /* ASRC Resampling Ratio Update Rate */ #define REG_EASRC_RUR(ctx) … /* ASRC Resampling Center Tap Coefficient Low */ #define REG_EASRC_RCTCL … /* ASRC Resampling Center Tap Coefficient High */ #define REG_EASRC_RCTCH … /* ASRC Prefilter Coefficient FIFO */ #define REG_EASRC_PCF(ctx) … /* ASRC Context Resampling Coefficient Memory */ #define REG_EASRC_CRCM … /* ASRC Context Resampling Coefficient Control*/ #define REG_EASRC_CRCC … /* ASRC Interrupt Control */ #define REG_EASRC_IRQC … /* ASRC Interrupt Status Flags */ #define REG_EASRC_IRQF … /* ASRC Channel Status 0 */ #define REG_EASRC_CS0(ctx) … /* ASRC Channel Status 1 */ #define REG_EASRC_CS1(ctx) … /* ASRC Channel Status 2 */ #define REG_EASRC_CS2(ctx) … /* ASRC Channel Status 3 */ #define REG_EASRC_CS3(ctx) … /* ASRC Channel Status 4 */ #define REG_EASRC_CS4(ctx) … /* ASRC Channel Status 5 */ #define REG_EASRC_CS5(ctx) … /* ASRC Debug Control Register */ #define REG_EASRC_DBGC … /* ASRC Debug Status Register */ #define REG_EASRC_DBGS … #define REG_EASRC_FIFO(x, ctx) … /* ASRC Context Control (CC) */ #define EASRC_CC_EN_SHIFT … #define EASRC_CC_EN_MASK … #define EASRC_CC_EN … #define EASRC_CC_STOP_SHIFT … #define EASRC_CC_STOP_MASK … #define EASRC_CC_STOP … #define EASRC_CC_FWMDE_SHIFT … #define EASRC_CC_FWMDE_MASK … #define EASRC_CC_FWMDE … #define EASRC_CC_FIFO_WTMK_SHIFT … #define EASRC_CC_FIFO_WTMK_WIDTH … #define EASRC_CC_FIFO_WTMK_MASK … #define EASRC_CC_FIFO_WTMK(v) … #define EASRC_CC_SAMPLE_POS_SHIFT … #define EASRC_CC_SAMPLE_POS_WIDTH … #define EASRC_CC_SAMPLE_POS_MASK … #define EASRC_CC_SAMPLE_POS(v) … #define EASRC_CC_ENDIANNESS_SHIFT … #define EASRC_CC_ENDIANNESS_MASK … #define EASRC_CC_ENDIANNESS … #define EASRC_CC_BPS_SHIFT … #define EASRC_CC_BPS_WIDTH … #define EASRC_CC_BPS_MASK … #define EASRC_CC_BPS(v) … #define EASRC_CC_FMT_SHIFT … #define EASRC_CC_FMT_MASK … #define EASRC_CC_FMT … #define EASRC_CC_INSIGN_SHIFT … #define EASRC_CC_INSIGN_MASK … #define EASRC_CC_INSIGN … #define EASRC_CC_CHEN_SHIFT … #define EASRC_CC_CHEN_WIDTH … #define EASRC_CC_CHEN_MASK … #define EASRC_CC_CHEN(v) … /* ASRC Context Control Extended 1 (CCE1) */ #define EASRC_CCE1_COEF_WS_SHIFT … #define EASRC_CCE1_COEF_WS_MASK … #define EASRC_CCE1_COEF_WS … #define EASRC_CCE1_COEF_MEM_RST_SHIFT … #define EASRC_CCE1_COEF_MEM_RST_MASK … #define EASRC_CCE1_COEF_MEM_RST … #define EASRC_CCE1_PF_EXP_SHIFT … #define EASRC_CCE1_PF_EXP_WIDTH … #define EASRC_CCE1_PF_EXP_MASK … #define EASRC_CCE1_PF_EXP(v) … #define EASRC_CCE1_PF_ST1_WBFP_SHIFT … #define EASRC_CCE1_PF_ST1_WBFP_MASK … #define EASRC_CCE1_PF_ST1_WBFP … #define EASRC_CCE1_PF_TSEN_SHIFT … #define EASRC_CCE1_PF_TSEN_MASK … #define EASRC_CCE1_PF_TSEN … #define EASRC_CCE1_RS_BYPASS_SHIFT … #define EASRC_CCE1_RS_BYPASS_MASK … #define EASRC_CCE1_RS_BYPASS … #define EASRC_CCE1_PF_BYPASS_SHIFT … #define EASRC_CCE1_PF_BYPASS_MASK … #define EASRC_CCE1_PF_BYPASS … #define EASRC_CCE1_RS_STOP_SHIFT … #define EASRC_CCE1_RS_STOP_MASK … #define EASRC_CCE1_RS_STOP … #define EASRC_CCE1_PF_STOP_SHIFT … #define EASRC_CCE1_PF_STOP_MASK … #define EASRC_CCE1_PF_STOP … #define EASRC_CCE1_RS_INIT_SHIFT … #define EASRC_CCE1_RS_INIT_WIDTH … #define EASRC_CCE1_RS_INIT_MASK … #define EASRC_CCE1_RS_INIT(v) … #define EASRC_CCE1_PF_INIT_SHIFT … #define EASRC_CCE1_PF_INIT_WIDTH … #define EASRC_CCE1_PF_INIT_MASK … #define EASRC_CCE1_PF_INIT(v) … /* ASRC Context Control Extended 2 (CCE2) */ #define EASRC_CCE2_ST2_TAPS_SHIFT … #define EASRC_CCE2_ST2_TAPS_WIDTH … #define EASRC_CCE2_ST2_TAPS_MASK … #define EASRC_CCE2_ST2_TAPS(v) … #define EASRC_CCE2_ST1_TAPS_SHIFT … #define EASRC_CCE2_ST1_TAPS_WIDTH … #define EASRC_CCE2_ST1_TAPS_MASK … #define EASRC_CCE2_ST1_TAPS(v) … /* ASRC Control Input Access (CIA) */ #define EASRC_CIA_ITER_SHIFT … #define EASRC_CIA_ITER_WIDTH … #define EASRC_CIA_ITER_MASK … #define EASRC_CIA_ITER(v) … #define EASRC_CIA_GRLEN_SHIFT … #define EASRC_CIA_GRLEN_WIDTH … #define EASRC_CIA_GRLEN_MASK … #define EASRC_CIA_GRLEN(v) … #define EASRC_CIA_ACCLEN_SHIFT … #define EASRC_CIA_ACCLEN_WIDTH … #define EASRC_CIA_ACCLEN_MASK … #define EASRC_CIA_ACCLEN(v) … /* ASRC Datapath Processor Control Slot0 Register0 (DPCS0R0) */ #define EASRC_DPCS0R0_MAXCH_SHIFT … #define EASRC_DPCS0R0_MAXCH_WIDTH … #define EASRC_DPCS0R0_MAXCH_MASK … #define EASRC_DPCS0R0_MAXCH(v) … #define EASRC_DPCS0R0_MINCH_SHIFT … #define EASRC_DPCS0R0_MINCH_WIDTH … #define EASRC_DPCS0R0_MINCH_MASK … #define EASRC_DPCS0R0_MINCH(v) … #define EASRC_DPCS0R0_NUMCH_SHIFT … #define EASRC_DPCS0R0_NUMCH_WIDTH … #define EASRC_DPCS0R0_NUMCH_MASK … #define EASRC_DPCS0R0_NUMCH(v) … #define EASRC_DPCS0R0_CTXNUM_SHIFT … #define EASRC_DPCS0R0_CTXNUM_WIDTH … #define EASRC_DPCS0R0_CTXNUM_MASK … #define EASRC_DPCS0R0_CTXNUM(v) … #define EASRC_DPCS0R0_EN_SHIFT … #define EASRC_DPCS0R0_EN_MASK … #define EASRC_DPCS0R0_EN … /* ASRC Datapath Processor Control Slot0 Register1 (DPCS0R1) */ #define EASRC_DPCS0R1_ST1_EXP_SHIFT … #define EASRC_DPCS0R1_ST1_EXP_WIDTH … #define EASRC_DPCS0R1_ST1_EXP_MASK … #define EASRC_DPCS0R1_ST1_EXP(v) … /* ASRC Datapath Processor Control Slot0 Register2 (DPCS0R2) */ #define EASRC_DPCS0R2_ST1_MA_SHIFT … #define EASRC_DPCS0R2_ST1_MA_WIDTH … #define EASRC_DPCS0R2_ST1_MA_MASK … #define EASRC_DPCS0R2_ST1_MA(v) … #define EASRC_DPCS0R2_ST1_SA_SHIFT … #define EASRC_DPCS0R2_ST1_SA_WIDTH … #define EASRC_DPCS0R2_ST1_SA_MASK … #define EASRC_DPCS0R2_ST1_SA(v) … /* ASRC Datapath Processor Control Slot0 Register3 (DPCS0R3) */ #define EASRC_DPCS0R3_ST2_MA_SHIFT … #define EASRC_DPCS0R3_ST2_MA_WIDTH … #define EASRC_DPCS0R3_ST2_MA_MASK … #define EASRC_DPCS0R3_ST2_MA(v) … #define EASRC_DPCS0R3_ST2_SA_SHIFT … #define EASRC_DPCS0R3_ST2_SA_WIDTH … #define EASRC_DPCS0R3_ST2_SA_MASK … #define EASRC_DPCS0R3_ST2_SA(v) … /* ASRC Context Output Control (COC) */ #define EASRC_COC_FWMDE_SHIFT … #define EASRC_COC_FWMDE_MASK … #define EASRC_COC_FWMDE … #define EASRC_COC_FIFO_WTMK_SHIFT … #define EASRC_COC_FIFO_WTMK_WIDTH … #define EASRC_COC_FIFO_WTMK_MASK … #define EASRC_COC_FIFO_WTMK(v) … #define EASRC_COC_SAMPLE_POS_SHIFT … #define EASRC_COC_SAMPLE_POS_WIDTH … #define EASRC_COC_SAMPLE_POS_MASK … #define EASRC_COC_SAMPLE_POS(v) … #define EASRC_COC_ENDIANNESS_SHIFT … #define EASRC_COC_ENDIANNESS_MASK … #define EASRC_COC_ENDIANNESS … #define EASRC_COC_BPS_SHIFT … #define EASRC_COC_BPS_WIDTH … #define EASRC_COC_BPS_MASK … #define EASRC_COC_BPS(v) … #define EASRC_COC_FMT_SHIFT … #define EASRC_COC_FMT_MASK … #define EASRC_COC_FMT … #define EASRC_COC_OUTSIGN_SHIFT … #define EASRC_COC_OUTSIGN_MASK … #define EASRC_COC_OUTSIGN_OUT … #define EASRC_COC_IEC_VDATA_SHIFT … #define EASRC_COC_IEC_VDATA_MASK … #define EASRC_COC_IEC_VDATA … #define EASRC_COC_IEC_EN_SHIFT … #define EASRC_COC_IEC_EN_MASK … #define EASRC_COC_IEC_EN … #define EASRC_COC_DITHER_EN_SHIFT … #define EASRC_COC_DITHER_EN_MASK … #define EASRC_COC_DITHER_EN … /* ASRC Control Output Access (COA) */ #define EASRC_COA_ITER_SHIFT … #define EASRC_COA_ITER_WIDTH … #define EASRC_COA_ITER_MASK … #define EASRC_COA_ITER(v) … #define EASRC_COA_GRLEN_SHIFT … #define EASRC_COA_GRLEN_WIDTH … #define EASRC_COA_GRLEN_MASK … #define EASRC_COA_GRLEN(v) … #define EASRC_COA_ACCLEN_SHIFT … #define EASRC_COA_ACCLEN_WIDTH … #define EASRC_COA_ACCLEN_MASK … #define EASRC_COA_ACCLEN(v) … /* ASRC Sample FIFO Status (SFS) */ #define EASRC_SFS_IWTMK_SHIFT … #define EASRC_SFS_IWTMK_MASK … #define EASRC_SFS_IWTMK … #define EASRC_SFS_NSGI_SHIFT … #define EASRC_SFS_NSGI_WIDTH … #define EASRC_SFS_NSGI_MASK … #define EASRC_SFS_NSGI(v) … #define EASRC_SFS_OWTMK_SHIFT … #define EASRC_SFS_OWTMK_MASK … #define EASRC_SFS_OWTMK … #define EASRC_SFS_NSGO_SHIFT … #define EASRC_SFS_NSGO_WIDTH … #define EASRC_SFS_NSGO_MASK … #define EASRC_SFS_NSGO(v) … /* ASRC Resampling Ratio Low (RRL) */ #define EASRC_RRL_RS_RL_SHIFT … #define EASRC_RRL_RS_RL_WIDTH … #define EASRC_RRL_RS_RL(v) … /* ASRC Resampling Ratio High (RRH) */ #define EASRC_RRH_RS_VLD_SHIFT … #define EASRC_RRH_RS_VLD_MASK … #define EASRC_RRH_RS_VLD … #define EASRC_RRH_RS_RH_SHIFT … #define EASRC_RRH_RS_RH_WIDTH … #define EASRC_RRH_RS_RH_MASK … #define EASRC_RRH_RS_RH(v) … /* ASRC Resampling Ratio Update Control (RSUC) */ #define EASRC_RSUC_RS_RM_SHIFT … #define EASRC_RSUC_RS_RM_WIDTH … #define EASRC_RSUC_RS_RM(v) … /* ASRC Resampling Ratio Update Rate (RRUR) */ #define EASRC_RRUR_RRR_SHIFT … #define EASRC_RRUR_RRR_WIDTH … #define EASRC_RRUR_RRR_MASK … #define EASRC_RRUR_RRR(v) … /* ASRC Resampling Center Tap Coefficient Low (RCTCL) */ #define EASRC_RCTCL_RS_CL_SHIFT … #define EASRC_RCTCL_RS_CL_WIDTH … #define EASRC_RCTCL_RS_CL(v) … /* ASRC Resampling Center Tap Coefficient High (RCTCH) */ #define EASRC_RCTCH_RS_CH_SHIFT … #define EASRC_RCTCH_RS_CH_WIDTH … #define EASRC_RCTCH_RS_CH(v) … /* ASRC Prefilter Coefficient FIFO (PCF) */ #define EASRC_PCF_CD_SHIFT … #define EASRC_PCF_CD_WIDTH … #define EASRC_PCF_CD(v) … /* ASRC Context Resampling Coefficient Memory (CRCM) */ #define EASRC_CRCM_RS_CWD_SHIFT … #define EASRC_CRCM_RS_CWD_WIDTH … #define EASRC_CRCM_RS_CWD(v) … /* ASRC Context Resampling Coefficient Control (CRCC) */ #define EASRC_CRCC_RS_CA_SHIFT … #define EASRC_CRCC_RS_CA_WIDTH … #define EASRC_CRCC_RS_CA_MASK … #define EASRC_CRCC_RS_CA(v) … #define EASRC_CRCC_RS_TAPS_SHIFT … #define EASRC_CRCC_RS_TAPS_WIDTH … #define EASRC_CRCC_RS_TAPS_MASK … #define EASRC_CRCC_RS_TAPS(v) … #define EASRC_CRCC_RS_CPR_SHIFT … #define EASRC_CRCC_RS_CPR_MASK … #define EASRC_CRCC_RS_CPR … /* ASRC Interrupt_Control (IC) */ #define EASRC_IRQC_RSDM_SHIFT … #define EASRC_IRQC_RSDM_WIDTH … #define EASRC_IRQC_RSDM_MASK … #define EASRC_IRQC_RSDM(v) … #define EASRC_IRQC_OERM_SHIFT … #define EASRC_IRQC_OERM_WIDTH … #define EASRC_IRQC_OERM_MASK … #define EASRC_IRQC_OERM(v) … #define EASRC_IRQC_IOM_SHIFT … #define EASRC_IRQC_IOM_WIDTH … #define EASRC_IRQC_IOM_MASK … #define EASRC_IRQC_IOM(v) … /* ASRC Interrupt Status Flags (ISF) */ #define EASRC_IRQF_RSD_SHIFT … #define EASRC_IRQF_RSD_WIDTH … #define EASRC_IRQF_RSD_MASK … #define EASRC_IRQF_RSD(v) … #define EASRC_IRQF_OER_SHIFT … #define EASRC_IRQF_OER_WIDTH … #define EASRC_IRQF_OER_MASK … #define EASRC_IRQF_OER(v) … #define EASRC_IRQF_IFO_SHIFT … #define EASRC_IRQF_IFO_WIDTH … #define EASRC_IRQF_IFO_MASK … #define EASRC_IRQF_IFO(v) … /* ASRC Context Channel STAT */ #define EASRC_CSx_CSx_SHIFT … #define EASRC_CSx_CSx_WIDTH … #define EASRC_CSx_CSx(v) … /* ASRC Debug Control Register */ #define EASRC_DBGC_DMS_SHIFT … #define EASRC_DBGC_DMS_WIDTH … #define EASRC_DBGC_DMS_MASK … #define EASRC_DBGC_DMS(v) … /* ASRC Debug Status Register */ #define EASRC_DBGS_DS_SHIFT … #define EASRC_DBGS_DS_WIDTH … #define EASRC_DBGS_DS(v) … /* General Constants */ #define EASRC_CTX_MAX_NUM … #define EASRC_RS_COEFF_MEM … #define EASRC_PF_COEFF_MEM … /* Prefilter constants */ #define EASRC_PF_ST1_ONLY … #define EASRC_PF_TWO_STAGE_MODE … #define EASRC_PF_ST1_COEFF_WR … #define EASRC_PF_ST2_COEFF_WR … #define EASRC_MAX_PF_TAPS … /* Resampling constants */ #define EASRC_RS_32_TAPS … #define EASRC_RS_64_TAPS … #define EASRC_RS_128_TAPS … /* Initialization mode */ #define EASRC_INIT_MODE_SW_CONTROL … #define EASRC_INIT_MODE_REPLICATE … #define EASRC_INIT_MODE_ZERO_FILL … /* FIFO watermarks */ #define FSL_EASRC_INPUTFIFO_WML … #define FSL_EASRC_OUTPUTFIFO_WML … #define EASRC_INPUTFIFO_THRESHOLD_MIN … #define EASRC_INPUTFIFO_THRESHOLD_MAX … #define EASRC_OUTPUTFIFO_THRESHOLD_MIN … #define EASRC_OUTPUTFIFO_THRESHOLD_MAX … #define EASRC_DMA_BUFFER_SIZE … #define EASRC_MAX_BUFFER_SIZE … #define FIRMWARE_MAGIC … #define FIRMWARE_VERSION … #define PREFILTER_MEM_LEN … enum easrc_word_width { … }; struct __attribute__((__packed__)) asrc_firmware_hdr { … }; struct __attribute__((__packed__)) interp_params { … }; struct __attribute__((__packed__)) prefil_params { … }; struct dma_block { … }; struct fsl_easrc_data_fmt { … }; struct fsl_easrc_io_params { … }; struct fsl_easrc_slot { … }; /** * fsl_easrc_ctx_priv: EASRC context private data * * @in_params: input parameter * @out_params: output parameter * @st1_num_taps: tap number of stage 1 * @st2_num_taps: tap number of stage 2 * @st1_num_exp: exponent number of stage 1 * @pf_init_mode: prefilter init mode * @rs_init_mode: resample filter init mode * @ctx_streams: stream flag of ctx * @rs_ratio: resampler ratio * @st1_coeff: pointer of stage 1 coeff * @st2_coeff: pointer of stage 2 coeff * @in_filled_sample: input filled sample * @out_missed_sample: sample missed in output * @st1_addexp: exponent added for stage1 * @st2_addexp: exponent added for stage2 */ struct fsl_easrc_ctx_priv { … }; /** * fsl_easrc_priv: EASRC private data * * @slot: slot setting * @firmware_hdr: the header of firmware * @interp: pointer to interpolation filter coeff * @prefil: pointer to prefilter coeff * @fw: firmware of coeff table * @fw_name: firmware name * @rs_num_taps: resample filter taps, 32, 64, or 128 * @bps_iec958: bits per sample of iec958 * @rs_coeff: resampler coefficient * @const_coeff: one tap prefilter coefficient * @firmware_loaded: firmware is loaded */ struct fsl_easrc_priv { … }; #endif /* _FSL_EASRC_H */
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