/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2020 NXP */ #ifndef _FSL_AUD2HTX_H #define _FSL_AUD2HTX_H #define FSL_AUD2HTX_FORMATS … /* AUD2HTX Register Map */ #define AUD2HTX_CTRL … #define AUD2HTX_CTRL_EXT … #define AUD2HTX_WR … #define AUD2HTX_STATUS … #define AUD2HTX_IRQ_NOMASK … #define AUD2HTX_IRQ_MASKED … #define AUD2HTX_IRQ_MASK … /* AUD2HTX Control Register */ #define AUD2HTX_CTRL_EN … /* AUD2HTX Control Extended Register */ #define AUD2HTX_CTRE_DE … #define AUD2HTX_CTRE_DT_SHIFT … #define AUD2HTX_CTRE_DT_WIDTH … #define AUD2HTX_CTRE_DT_MASK … #define AUD2HTX_CTRE_WL_SHIFT … #define AUD2HTX_CTRE_WL_WIDTH … #define AUD2HTX_CTRE_WL_MASK … #define AUD2HTX_CTRE_WH_SHIFT … #define AUD2HTX_CTRE_WH_WIDTH … #define AUD2HTX_CTRE_WH_MASK … /* AUD2HTX IRQ Masks Register */ #define AUD2HTX_WM_HIGH_IRQ_MASK … #define AUD2HTX_WM_LOW_IRQ_MASK … #define AUD2HTX_OVF_MASK … #define AUD2HTX_FIFO_DEPTH … #define AUD2HTX_WTMK_LOW … #define AUD2HTX_WTMK_HIGH … #define AUD2HTX_MAXBURST … /** * fsl_aud2htx: AUD2HTX private data * * @pdev: platform device pointer * @regmap: regmap handler * @bus_clk: clock source to access register * @dma_params_rx: DMA parameters for receive channel * @dma_params_tx: DMA parameters for transmit channel */ struct fsl_aud2htx { … }; #endif /* _FSL_AUD2HTX_H */
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