linux/drivers/clk/renesas/clk-div6.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a7790 Common Clock Framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 *
 * Contact: Laurent Pinchart <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm.h>
#include <linux/slab.h>

#include "clk-div6.h"

#define CPG_DIV6_CKSTP …
#define CPG_DIV6_DIV(d) …
#define CPG_DIV6_DIV_MASK …

/**
 * struct div6_clock - CPG 6 bit divider clock
 * @hw: handle between common and hardware-specific interfaces
 * @reg: IO-remapped register
 * @div: divisor value (1-64)
 * @src_mask: Bitmask covering the register bits to select the parent clock
 * @nb: Notifier block to save/restore clock state for system resume
 * @parents: Array to map from valid parent clocks indices to hardware indices
 */
struct div6_clock { … };

#define to_div6_clock(_hw) …

static int cpg_div6_clock_enable(struct clk_hw *hw)
{ … }

static void cpg_div6_clock_disable(struct clk_hw *hw)
{ … }

static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
{ … }

static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{ … }

static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
					    unsigned long parent_rate)
{ … }

static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
					 struct clk_rate_request *req)
{ … }

static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{ … }

static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
{ … }

static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
{ … }

static const struct clk_ops cpg_div6_clock_ops = …;

static int cpg_div6_clock_notifier_call(struct notifier_block *nb,
					unsigned long action, void *data)
{ … }

/**
 * cpg_div6_register - Register a DIV6 clock
 * @name: Name of the DIV6 clock
 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
 * @parent_names: Array containing the names of the parent clocks
 * @reg: Mapped register used to control the DIV6 clock
 * @notifiers: Optional notifier chain to save/restore state for system resume
 */
struct clk * __init cpg_div6_register(const char *name,
				      unsigned int num_parents,
				      const char **parent_names,
				      void __iomem *reg,
				      struct raw_notifier_head *notifiers)
{ … }

static void __init cpg_div6_clock_init(struct device_node *np)
{ … }
CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);