/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/sound/soc/hisilicon/hi6210-i2s.h * * Copyright (C) 2015 Linaro, Ltd * Author: Andy Green <[email protected]> * * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF */ #ifndef _HI6210_I2S_H #define _HI6210_I2S_H #define HII2S_SW_RST_N … #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT … #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK … #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT … #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK … #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT … #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK … #define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT … #define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK … #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT … #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK … #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT … #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK … #define HII2S_SW_RST_N__SW_RST_N … enum hi6210_bits { … }; #define HII2S_IF_CLK_EN_CFG … #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN … #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN … #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN … #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN … #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN … #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN … #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN … #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN … #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN … #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN … #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN … #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN … #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN … #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN … #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN … #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN … #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN … #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN … #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN … #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN … #define HII2S_FS_CFG … #define HII2S_FS_CFG__FS_S2_SHIFT … #define HII2S_FS_CFG__FS_S2_MASK … #define HII2S_FS_CFG__FS_S1_SHIFT … #define HII2S_FS_CFG__FS_S1_MASK … #define HII2S_FS_CFG__FS_ADCLR_SHIFT … #define HII2S_FS_CFG__FS_ADCLR_MASK … #define HII2S_FS_CFG__FS_DACLR_SHIFT … #define HII2S_FS_CFG__FS_DACLR_MASK … #define HII2S_FS_CFG__FS_ST_DL_R_SHIFT … #define HII2S_FS_CFG__FS_ST_DL_R_MASK … #define HII2S_FS_CFG__FS_ST_DL_L_SHIFT … #define HII2S_FS_CFG__FS_ST_DL_L_MASK … #define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT … #define HII2S_FS_CFG__FS_VOICE_DLINK_MASK … enum hi6210_i2s_rates { … }; #define HII2S_I2S_CFG … #define HII2S_I2S_CFG__S2_IF_TX_EN … #define HII2S_I2S_CFG__S2_IF_RX_EN … #define HII2S_I2S_CFG__S2_FRAME_MODE … #define HII2S_I2S_CFG__S2_MST_SLV … #define HII2S_I2S_CFG__S2_LRCK_MODE … #define HII2S_I2S_CFG__S2_CHNNL_MODE … #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT … #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK … #define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT … #define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK … #define HII2S_I2S_CFG__S2_TX_CLK_SEL … #define HII2S_I2S_CFG__S2_RX_CLK_SEL … #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT … #define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT … #define HII2S_I2S_CFG__S2_FUNC_MODE_MASK … #define HII2S_I2S_CFG__S1_IF_TX_EN … #define HII2S_I2S_CFG__S1_IF_RX_EN … #define HII2S_I2S_CFG__S1_FRAME_MODE … #define HII2S_I2S_CFG__S1_MST_SLV … #define HII2S_I2S_CFG__S1_LRCK_MODE … #define HII2S_I2S_CFG__S1_CHNNL_MODE … #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT … #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK … #define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT … #define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK … #define HII2S_I2S_CFG__S1_TX_CLK_SEL … #define HII2S_I2S_CFG__S1_RX_CLK_SEL … #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT … #define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT … #define HII2S_I2S_CFG__S1_FUNC_MODE_MASK … enum hi6210_i2s_formats { … }; #define HII2S_DIG_FILTER_MODULE_CFG … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE … #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER … #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER … #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT … #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK … #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT … #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK … enum hi6210_gains { … }; #define HII2S_MUX_TOP_MODULE_CFG … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT … #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT … #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK … enum hi6210_s2_src_mode { … }; enum hi6210_voice_dlink_src_mode { … }; #define HII2S_ADC_PGA_CFG … #define HII2S_S1_INPUT_PGA_CFG … #define HII2S_S2_INPUT_PGA_CFG … #define HII2S_ST_DL_PGA_CFG … #define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG … #define HII2S_APB_AFIFO_CFG_1 … #define HII2S_APB_AFIFO_CFG_2 … #define HII2S_ST_DL_FIFO_TH_CFG … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT … #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK … #define HII2S_STEREO_UPLINK_FIFO_TH_CFG … #define HII2S_VOICE_UPLINK_FIFO_TH_CFG … #define HII2S_CODEC_IRQ_MASK … #define HII2S_CODEC_IRQ … #define HII2S_DACL_AGC_CFG_1 … #define HII2S_DACL_AGC_CFG_2 … #define HII2S_DACR_AGC_CFG_1 … #define HII2S_DACR_AGC_CFG_2 … #define HII2S_DMIC_SIF_CFG … #define HII2S_MISC_CFG … #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL … #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL … #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL … #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL … #define HII2S_MISC_CFG__S3_DIN_TEST_SEL … #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL … #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL … #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL … #define HII2S_MISC_CFG__ST_DL_TEST_SEL … #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL … #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL … #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL … #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL … #define HII2S_S2_SRC_CFG … #define HII2S_MEM_CFG … #define HII2S_THIRDMD_PCM_PGA_CFG … #define HII2S_THIRD_MODEM_FIFO_TH … #define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT … #define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT … #define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT … #define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT … #define HII2S_ANTI_FREQ_JITTER_EN … #define HII2S_CLK_SEL … /* 0 = BT owns the i2s */ #define HII2S_CLK_SEL__I2S_BT_FM_SEL … /* 0 = internal source, 1 = ext */ #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL … #define HII2S_THIRDMD_DLINK_CHANNEL … #define HII2S_THIRDMD_ULINK_CHANNEL … #define HII2S_VOICE_DLINK_CHANNEL … /* shovel data in here for playback */ #define HII2S_ST_DL_CHANNEL … #define HII2S_STEREO_UPLINK_CHANNEL … #define HII2S_VOICE_UPLINK_CHANNEL … #endif/* _HI6210_I2S_H */
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