/* SPDX-License-Identifier: GPL-2.0-only */ /* * Intel Code Loader DMA support * * Copyright (C) 2015, Intel Corporation. */ #ifndef SKL_SST_CLDMA_H_ #define SKL_SST_CLDMA_H_ #define FW_CL_STREAM_NUMBER … #define DMA_ADDRESS_128_BITS_ALIGNMENT … #define BDL_ALIGN(x) … #define SKL_ADSPIC_CL_DMA … #define SKL_ADSPIS_CL_DMA … #define SKL_CL_DMA_SD_INT_DESC_ERR … #define SKL_CL_DMA_SD_INT_FIFO_ERR … #define SKL_CL_DMA_SD_INT_COMPLETE … /* Intel HD Audio Code Loader DMA Registers */ #define HDA_ADSP_LOADER_BASE … /* Stream Registers */ #define SKL_ADSP_REG_CL_SD_CTL … #define SKL_ADSP_REG_CL_SD_STS … #define SKL_ADSP_REG_CL_SD_LPIB … #define SKL_ADSP_REG_CL_SD_CBL … #define SKL_ADSP_REG_CL_SD_LVI … #define SKL_ADSP_REG_CL_SD_FIFOW … #define SKL_ADSP_REG_CL_SD_FIFOSIZE … #define SKL_ADSP_REG_CL_SD_FORMAT … #define SKL_ADSP_REG_CL_SD_FIFOL … #define SKL_ADSP_REG_CL_SD_BDLPL … #define SKL_ADSP_REG_CL_SD_BDLPU … /* CL: Software Position Based FIFO Capability Registers */ #define SKL_ADSP_REG_CL_SPBFIFO … #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH … #define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL … #define SKL_ADSP_REG_CL_SPBFIFO_SPIB … #define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS … /* CL: Stream Descriptor x Control */ /* Stream Reset */ #define CL_SD_CTL_SRST_SHIFT … #define CL_SD_CTL_SRST_MASK … #define CL_SD_CTL_SRST(x) … /* Stream Run */ #define CL_SD_CTL_RUN_SHIFT … #define CL_SD_CTL_RUN_MASK … #define CL_SD_CTL_RUN(x) … /* Interrupt On Completion Enable */ #define CL_SD_CTL_IOCE_SHIFT … #define CL_SD_CTL_IOCE_MASK … #define CL_SD_CTL_IOCE(x) … /* FIFO Error Interrupt Enable */ #define CL_SD_CTL_FEIE_SHIFT … #define CL_SD_CTL_FEIE_MASK … #define CL_SD_CTL_FEIE(x) … /* Descriptor Error Interrupt Enable */ #define CL_SD_CTL_DEIE_SHIFT … #define CL_SD_CTL_DEIE_MASK … #define CL_SD_CTL_DEIE(x) … /* FIFO Limit Change */ #define CL_SD_CTL_FIFOLC_SHIFT … #define CL_SD_CTL_FIFOLC_MASK … #define CL_SD_CTL_FIFOLC(x) … /* Stripe Control */ #define CL_SD_CTL_STRIPE_SHIFT … #define CL_SD_CTL_STRIPE_MASK … #define CL_SD_CTL_STRIPE(x) … /* Traffic Priority */ #define CL_SD_CTL_TP_SHIFT … #define CL_SD_CTL_TP_MASK … #define CL_SD_CTL_TP(x) … /* Bidirectional Direction Control */ #define CL_SD_CTL_DIR_SHIFT … #define CL_SD_CTL_DIR_MASK … #define CL_SD_CTL_DIR(x) … /* Stream Number */ #define CL_SD_CTL_STRM_SHIFT … #define CL_SD_CTL_STRM_MASK … #define CL_SD_CTL_STRM(x) … /* CL: Stream Descriptor x Status */ /* Buffer Completion Interrupt Status */ #define CL_SD_STS_BCIS(x) … /* FIFO Error */ #define CL_SD_STS_FIFOE(x) … /* Descriptor Error */ #define CL_SD_STS_DESE(x) … /* FIFO Ready */ #define CL_SD_STS_FIFORDY(x) … /* CL: Stream Descriptor x Last Valid Index */ #define CL_SD_LVI_SHIFT … #define CL_SD_LVI_MASK … #define CL_SD_LVI(x) … /* CL: Stream Descriptor x FIFO Eviction Watermark */ #define CL_SD_FIFOW_SHIFT … #define CL_SD_FIFOW_MASK … #define CL_SD_FIFOW(x) … /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */ /* Protect Bits */ #define CL_SD_BDLPLBA_PROT_SHIFT … #define CL_SD_BDLPLBA_PROT_MASK … #define CL_SD_BDLPLBA_PROT(x) … /* Buffer Descriptor List Lower Base Address */ #define CL_SD_BDLPLBA_SHIFT … #define CL_SD_BDLPLBA_MASK … #define CL_SD_BDLPLBA(x) … /* Buffer Descriptor List Upper Base Address */ #define CL_SD_BDLPUBA_SHIFT … #define CL_SD_BDLPUBA_MASK … #define CL_SD_BDLPUBA(x) … /* * Code Loader - Software Position Based FIFO * Capability Registers x Software Position Based FIFO Header */ /* Next Capability Pointer */ #define CL_SPBFIFO_SPBFCH_PTR_SHIFT … #define CL_SPBFIFO_SPBFCH_PTR_MASK … #define CL_SPBFIFO_SPBFCH_PTR(x) … /* Capability Identifier */ #define CL_SPBFIFO_SPBFCH_ID_SHIFT … #define CL_SPBFIFO_SPBFCH_ID_MASK … #define CL_SPBFIFO_SPBFCH_ID(x) … /* Capability Version */ #define CL_SPBFIFO_SPBFCH_VER_SHIFT … #define CL_SPBFIFO_SPBFCH_VER_MASK … #define CL_SPBFIFO_SPBFCH_VER(x) … /* Software Position in Buffer Enable */ #define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT … #define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK … #define CL_SPBFIFO_SPBFCCTL_SPIBE(x) … /* SST IPC SKL defines */ #define SKL_WAIT_TIMEOUT … #define SKL_MAX_BUFFER_SIZE … enum skl_cl_dma_wake_states { … }; struct sst_dsp; struct skl_cl_dev_ops { … }; /** * skl_cl_dev - holds information for code loader dma transfer * * @dmab_data: buffer pointer * @dmab_bdl: buffer descriptor list * @bufsize: ring buffer size * @frags: Last valid buffer descriptor index in the BDL * @curr_spib_pos: Current position in ring buffer * @dma_buffer_offset: dma buffer offset * @ops: operations supported on CL dma * @wait_queue: wait queue to wake for wake event * @wake_status: DMA wake status * @wait_condition: condition to wait on wait queue * @cl_dma_lock: for synchronized access to cldma */ struct skl_cl_dev { … }; #endif /* SKL_SST_CLDMA_H_ */
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