/* SPDX-License-Identifier: GPL-2.0-only */ /* * Skylake SST DSP Support * * Copyright (C) 2014-15, Intel Corporation. */ #ifndef __SKL_SST_DSP_H__ #define __SKL_SST_DSP_H__ #include <linux/interrupt.h> #include <linux/uuid.h> #include <linux/firmware.h> #include <sound/memalloc.h> #include "skl-sst-cldma.h" struct sst_dsp; struct sst_dsp_device; struct skl_lib_info; struct skl_dev; /* Intel HD Audio General DSP Registers */ #define SKL_ADSP_GEN_BASE … #define SKL_ADSP_REG_ADSPCS … #define SKL_ADSP_REG_ADSPIC … #define SKL_ADSP_REG_ADSPIS … #define SKL_ADSP_REG_ADSPIC2 … #define SKL_ADSP_REG_ADSPIS2 … /* Intel HD Audio Inter-Processor Communication Registers */ #define SKL_ADSP_IPC_BASE … #define SKL_ADSP_REG_HIPCT … #define SKL_ADSP_REG_HIPCTE … #define SKL_ADSP_REG_HIPCI … #define SKL_ADSP_REG_HIPCIE … #define SKL_ADSP_REG_HIPCCTL … /* HIPCI */ #define SKL_ADSP_REG_HIPCI_BUSY … /* HIPCIE */ #define SKL_ADSP_REG_HIPCIE_DONE … /* HIPCCTL */ #define SKL_ADSP_REG_HIPCCTL_DONE … #define SKL_ADSP_REG_HIPCCTL_BUSY … /* HIPCT */ #define SKL_ADSP_REG_HIPCT_BUSY … /* FW base IDs */ #define SKL_INSTANCE_ID … #define SKL_BASE_FW_MODULE_ID … /* Intel HD Audio SRAM Window 1 */ #define SKL_ADSP_SRAM1_BASE … #define SKL_ADSP_MMIO_LEN … #define SKL_ADSP_W0_STAT_SZ … #define SKL_ADSP_W0_UP_SZ … #define SKL_ADSP_W1_SZ … #define SKL_FW_STS_MASK … #define SKL_FW_INIT … #define SKL_FW_RFW_START … #define BXT_FW_ROM_INIT_RETRY … #define BXT_INIT_TIMEOUT … #define SKL_ADSPIC_IPC … #define SKL_ADSPIS_IPC … /* Core ID of core0 */ #define SKL_DSP_CORE0_ID … /* Mask for a given core index, c = 0.. number of supported cores - 1 */ #define SKL_DSP_CORE_MASK(c) … /* * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately * since Core0 is primary core and it is used often */ #define SKL_DSP_CORE0_MASK … /* * Mask for a given number of cores * nc = number of supported cores */ #define SKL_DSP_CORES_MASK(nc) … /* ADSPCS - Audio DSP Control & Status */ /* * Core Reset - asserted high * CRST Mask for a given core mask pattern, cm */ #define SKL_ADSPCS_CRST_SHIFT … #define SKL_ADSPCS_CRST_MASK(cm) … /* * Core run/stall - when set to '1' core is stalled * CSTALL Mask for a given core mask pattern, cm */ #define SKL_ADSPCS_CSTALL_SHIFT … #define SKL_ADSPCS_CSTALL_MASK(cm) … /* * Set Power Active - when set to '1' turn cores on * SPA Mask for a given core mask pattern, cm */ #define SKL_ADSPCS_SPA_SHIFT … #define SKL_ADSPCS_SPA_MASK(cm) … /* * Current Power Active - power status of cores, set by hardware * CPA Mask for a given core mask pattern, cm */ #define SKL_ADSPCS_CPA_SHIFT … #define SKL_ADSPCS_CPA_MASK(cm) … /* DSP Core state */ enum skl_dsp_states { … }; /* D0i3 substates */ enum skl_dsp_d0i3_states { … }; struct skl_dsp_fw_ops { … }; struct skl_dsp_loader_ops { … }; #define MAX_INSTANCE_BUFF … struct uuid_module { … }; struct skl_load_module_info { … }; struct skl_module_table { … }; void skl_cldma_process_intr(struct sst_dsp *ctx); void skl_cldma_int_disable(struct sst_dsp *ctx); int skl_cldma_prepare(struct sst_dsp *ctx); int skl_cldma_wait_interruptible(struct sst_dsp *ctx); void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); struct sst_dsp *skl_dsp_ctx_init(struct device *dev, struct sst_dsp_device *sst_dev, int irq); int skl_dsp_acquire_irq(struct sst_dsp *sst); bool is_skl_dsp_running(struct sst_dsp *ctx); unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); void skl_dsp_init_core_state(struct sst_dsp *ctx); int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, unsigned int core_mask); int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); int skl_dsp_wake(struct sst_dsp *ctx); int skl_dsp_sleep(struct sst_dsp *ctx); void skl_dsp_free(struct sst_dsp *dsp); int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); int skl_dsp_boot(struct sst_dsp *ctx); int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, const char *fw_name, struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp); int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, const char *fw_name, struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp); int skl_sst_init_fw(struct device *dev, struct skl_dev *skl); int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl); void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, unsigned int offset, int index); int skl_get_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int instance_id); int skl_put_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int *pvt_id); int skl_get_pvt_instance_id_map(struct skl_dev *skl, int module_id, int instance_id); void skl_freeup_uuid_list(struct skl_dev *skl); int skl_dsp_strip_extended_manifest(struct firmware *fw); void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data); int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name, struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp, struct sst_dsp_device *skl_dev); int skl_prepare_lib_load(struct skl_dev *skl, struct skl_lib_info *linfo, struct firmware *stripped_fw, unsigned int hdr_offset, int index); void skl_release_library(struct skl_lib_info *linfo, int lib_count); #endif /*__SKL_SST_DSP_H__*/
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