linux/sound/soc/intel/skylake/skl-ssp-clk.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  skl-ssp-clk.h - Skylake ssp clock information and ipc structure
 *
 *  Copyright (C) 2017 Intel Corp
 *  Author: Jaikrishna Nemallapudi <[email protected]>
 *  Author: Subhransu S. Prusty <[email protected]>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */

#ifndef SOUND_SOC_SKL_SSP_CLK_H
#define SOUND_SOC_SKL_SSP_CLK_H

#define SKL_MAX_SSP …
/* xtal/cardinal/pll, parent of ssp clocks and mclk */
#define SKL_MAX_CLK_SRC …
#define SKL_MAX_SSP_CLK_TYPES …

#define SKL_MAX_CLK_CNT …

/* Max number of configurations supported for each clock */
#define SKL_MAX_CLK_RATES …

#define SKL_SCLK_OFS …
#define SKL_SCLKFS_OFS …

enum skl_clk_type { … };

enum skl_clk_src_type { … };

struct skl_clk_parent_src { … };

struct skl_tlv_hdr { … };

struct skl_dmactrl_mclk_cfg { … };

struct skl_dmactrl_sclkfs_cfg { … };

skl_clk_ctrl_ipc;

struct skl_clk_rate_cfg_table { … };

/*
 * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
 * all possible clocks ssp can generate for that platform.
 */
struct skl_ssp_clk { … };

struct skl_clk_pdata { … };

#endif /* SOUND_SOC_SKL_SSP_CLK_H */