linux/drivers/clk/renesas/r9a09g011-cpg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 *
 * Based on r9a07g044-cpg.c
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <dt-bindings/clock/r9a09g011-cpg.h>

#include "rzg2l-cpg.h"

#define RZV2M_SAMPLL4_CLK1 …
#define RZV2M_SAMPLL4_CLK2 …

#define PLL4_CONF …

#define DIV_A …
#define DIV_B …
#define DIV_D …
#define DIV_E …
#define DIV_W …

#define SEL_B …
#define SEL_CSI0 …
#define SEL_CSI4 …
#define SEL_D …
#define SEL_E …
#define SEL_SDI …
#define SEL_W0 …

enum clk_ids { … };

/* Divider tables */
static const struct clk_div_table dtable_diva[] = …;

static const struct clk_div_table dtable_divb[] = …;

static const struct clk_div_table dtable_divd[] = …;


static const struct clk_div_table dtable_divw[] = …;

/* Mux clock tables */
static const char * const sel_b[] = …;
static const char * const sel_csi[] = …;
static const char * const sel_d[] = …;
static const char * const sel_e[] = …;
static const char * const sel_w[] = …;
static const char * const sel_sdi[] = …;

static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = …;

static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = …;

static const struct rzg2l_reset r9a09g011_resets[] = …;

static const unsigned int r9a09g011_crit_mod_clks[] __initconst = …;

const struct rzg2l_cpg_info r9a09g011_cpg_info = …;