linux/include/dt-bindings/clock/exynos5250.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Andrzej Hajda <[email protected]>
 *
 * Device Tree binding constants for Exynos5250 clock controller.
 */

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H

/* core clocks */
#define CLK_FIN_PLL
#define CLK_FOUT_APLL
#define CLK_FOUT_MPLL
#define CLK_FOUT_BPLL
#define CLK_FOUT_GPLL
#define CLK_FOUT_CPLL
#define CLK_FOUT_EPLL
#define CLK_FOUT_VPLL
#define CLK_ARM_CLK
#define CLK_DIV_ARM2

/* gate for special clocks (sclk) */
#define CLK_SCLK_CAM_BAYER
#define CLK_SCLK_CAM0
#define CLK_SCLK_CAM1
#define CLK_SCLK_GSCL_WA
#define CLK_SCLK_GSCL_WB
#define CLK_SCLK_FIMD1
#define CLK_SCLK_MIPI1
#define CLK_SCLK_DP
#define CLK_SCLK_HDMI
#define CLK_SCLK_PIXEL
#define CLK_SCLK_AUDIO0
#define CLK_SCLK_MMC0
#define CLK_SCLK_MMC1
#define CLK_SCLK_MMC2
#define CLK_SCLK_MMC3
#define CLK_SCLK_SATA
#define CLK_SCLK_USB3
#define CLK_SCLK_JPEG
#define CLK_SCLK_UART0
#define CLK_SCLK_UART1
#define CLK_SCLK_UART2
#define CLK_SCLK_UART3
#define CLK_SCLK_PWM
#define CLK_SCLK_AUDIO1
#define CLK_SCLK_AUDIO2
#define CLK_SCLK_SPDIF
#define CLK_SCLK_SPI0
#define CLK_SCLK_SPI1
#define CLK_SCLK_SPI2
#define CLK_DIV_I2S1
#define CLK_DIV_I2S2
#define CLK_SCLK_HDMIPHY
#define CLK_DIV_PCM0

/* gate clocks */
#define CLK_GSCL0
#define CLK_GSCL1
#define CLK_GSCL2
#define CLK_GSCL3
#define CLK_GSCL_WA
#define CLK_GSCL_WB
#define CLK_SMMU_GSCL0
#define CLK_SMMU_GSCL1
#define CLK_SMMU_GSCL2
#define CLK_SMMU_GSCL3
#define CLK_MFC
#define CLK_SMMU_MFCL
#define CLK_SMMU_MFCR
#define CLK_ROTATOR
#define CLK_JPEG
#define CLK_MDMA1
#define CLK_SMMU_ROTATOR
#define CLK_SMMU_JPEG
#define CLK_SMMU_MDMA1
#define CLK_PDMA0
#define CLK_PDMA1
#define CLK_SATA
#define CLK_USBOTG
#define CLK_MIPI_HSI
#define CLK_SDMMC0
#define CLK_SDMMC1
#define CLK_SDMMC2
#define CLK_SDMMC3
#define CLK_SROMC
#define CLK_USB2
#define CLK_USB3
#define CLK_SATA_PHYCTRL
#define CLK_SATA_PHYI2C
#define CLK_UART0
#define CLK_UART1
#define CLK_UART2
#define CLK_UART3
#define CLK_UART4
#define CLK_I2C0
#define CLK_I2C1
#define CLK_I2C2
#define CLK_I2C3
#define CLK_I2C4
#define CLK_I2C5
#define CLK_I2C6
#define CLK_I2C7
#define CLK_I2C_HDMI
#define CLK_ADC
#define CLK_SPI0
#define CLK_SPI1
#define CLK_SPI2
#define CLK_I2S1
#define CLK_I2S2
#define CLK_PCM1
#define CLK_PCM2
#define CLK_PWM
#define CLK_SPDIF
#define CLK_AC97
#define CLK_HSI2C0
#define CLK_HSI2C1
#define CLK_HSI2C2
#define CLK_HSI2C3
#define CLK_CHIPID
#define CLK_SYSREG
#define CLK_PMU
#define CLK_CMU_TOP
#define CLK_CMU_CORE
#define CLK_CMU_MEM
#define CLK_TZPC0
#define CLK_TZPC1
#define CLK_TZPC2
#define CLK_TZPC3
#define CLK_TZPC4
#define CLK_TZPC5
#define CLK_TZPC6
#define CLK_TZPC7
#define CLK_TZPC8
#define CLK_TZPC9
#define CLK_HDMI_CEC
#define CLK_MCT
#define CLK_WDT
#define CLK_RTC
#define CLK_TMU
#define CLK_FIMD1
#define CLK_MIE1
#define CLK_DSIM0
#define CLK_DP
#define CLK_MIXER
#define CLK_HDMI
#define CLK_G2D
#define CLK_MDMA0
#define CLK_SMMU_MDMA0
#define CLK_SSS
#define CLK_G3D
#define CLK_SMMU_TV
#define CLK_SMMU_FIMD1
#define CLK_SMMU_2D
#define CLK_SMMU_FIMC_ISP
#define CLK_SMMU_FIMC_DRC
#define CLK_SMMU_FIMC_SCC
#define CLK_SMMU_FIMC_SCP
#define CLK_SMMU_FIMC_FD
#define CLK_SMMU_FIMC_MCU
#define CLK_SMMU_FIMC_ODC
#define CLK_SMMU_FIMC_DIS0
#define CLK_SMMU_FIMC_DIS1
#define CLK_SMMU_FIMC_3DNR
#define CLK_SMMU_FIMC_LITE0
#define CLK_SMMU_FIMC_LITE1
#define CLK_CAMIF_TOP

/* mux clocks */
#define CLK_MOUT_HDMI
#define CLK_MOUT_GPLL
#define CLK_MOUT_ACLK200_DISP1_SUB
#define CLK_MOUT_ACLK300_DISP1_SUB
#define CLK_MOUT_APLL
#define CLK_MOUT_MPLL
#define CLK_MOUT_VPLLSRC

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */