// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * * Common Clock Framework support for Exynos3250 SoC. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <dt-bindings/clock/exynos3250.h> #include "clk.h" #include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS … #define DIV_LEFTBUS … #define GATE_IP_LEFTBUS … #define SRC_RIGHTBUS … #define DIV_RIGHTBUS … #define GATE_IP_RIGHTBUS … #define GATE_IP_PERIR … #define MPLL_LOCK … #define MPLL_CON0 … #define VPLL_LOCK … #define VPLL_CON0 … #define UPLL_LOCK … #define UPLL_CON0 … #define SRC_TOP0 … #define SRC_TOP1 … #define SRC_CAM … #define SRC_MFC … #define SRC_G3D … #define SRC_LCD … #define SRC_ISP … #define SRC_FSYS … #define SRC_PERIL0 … #define SRC_PERIL1 … #define SRC_MASK_TOP … #define SRC_MASK_CAM … #define SRC_MASK_LCD … #define SRC_MASK_ISP … #define SRC_MASK_FSYS … #define SRC_MASK_PERIL0 … #define SRC_MASK_PERIL1 … #define DIV_TOP … #define DIV_CAM … #define DIV_MFC … #define DIV_G3D … #define DIV_LCD … #define DIV_ISP … #define DIV_FSYS0 … #define DIV_FSYS1 … #define DIV_FSYS2 … #define DIV_PERIL0 … #define DIV_PERIL1 … #define DIV_PERIL3 … #define DIV_PERIL4 … #define DIV_PERIL5 … #define DIV_CAM1 … #define CLKDIV2_RATIO … #define GATE_SCLK_CAM … #define GATE_SCLK_MFC … #define GATE_SCLK_G3D … #define GATE_SCLK_LCD … #define GATE_SCLK_ISP_TOP … #define GATE_SCLK_FSYS … #define GATE_SCLK_PERIL … #define GATE_IP_CAM … #define GATE_IP_MFC … #define GATE_IP_G3D … #define GATE_IP_LCD … #define GATE_IP_ISP … #define GATE_IP_FSYS … #define GATE_IP_PERIL … #define GATE_BLOCK … #define APLL_LOCK … #define APLL_CON0 … #define SRC_CPU … #define DIV_CPU0 … #define DIV_CPU1 … #define PWR_CTRL1 … #define PWR_CTRL2 … /* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) … #define PWR_CTRL1_CORE1_DOWN_RATIO(x) … #define PWR_CTRL1_DIV2_DOWN_EN … #define PWR_CTRL1_DIV1_DOWN_EN … #define PWR_CTRL1_USE_CORE3_WFE … #define PWR_CTRL1_USE_CORE2_WFE … #define PWR_CTRL1_USE_CORE1_WFE … #define PWR_CTRL1_USE_CORE0_WFE … #define PWR_CTRL1_USE_CORE3_WFI … #define PWR_CTRL1_USE_CORE2_WFI … #define PWR_CTRL1_USE_CORE1_WFI … #define PWR_CTRL1_USE_CORE0_WFI … /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_MAIN … #define CLKS_NR_DMC … #define CLKS_NR_ISP … static const unsigned long exynos3250_cmu_clk_regs[] __initconst = …; /* list of all parent clock list */ PNAME(mout_vpllsrc_p) = …; PNAME(mout_apll_p) = …; PNAME(mout_mpll_p) = …; PNAME(mout_vpll_p) = …; PNAME(mout_upll_p) = …; PNAME(mout_mpll_user_p) = …; PNAME(mout_epll_user_p) = …; PNAME(mout_core_p) = …; PNAME(mout_hpm_p) = …; PNAME(mout_ebi_p) = …; PNAME(mout_ebi_1_p) = …; PNAME(mout_gdl_p) = …; PNAME(mout_gdr_p) = …; PNAME(mout_aclk_400_mcuisp_sub_p) = …; PNAME(mout_aclk_266_0_p) = …; PNAME(mout_aclk_266_1_p) = …; PNAME(mout_aclk_266_p) = …; PNAME(mout_aclk_266_sub_p) = …; PNAME(group_div_mpll_pre_p) = …; PNAME(group_epll_vpll_p) = …; PNAME(group_sclk_p) = …; PNAME(group_sclk_audio_p) = …; PNAME(group_sclk_cam_blk_p) = …; PNAME(group_sclk_fimd0_p) = …; PNAME(mout_mfc_p) = …; PNAME(mout_g3d_p) = …; static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = …; static const struct samsung_mux_clock mux_clks[] __initconst = …; static const struct samsung_div_clock div_clks[] __initconst = …; static const struct samsung_gate_clock gate_clks[] __initconst = …; /* APLL & MPLL & BPLL & UPLL */ static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = …; /* EPLL */ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = …; /* VPLL */ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = …; static const struct samsung_pll_clock exynos3250_plls[] __initconst = …; #define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) … #define E3250_CPU_DIV1(hpm, copy) … static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = …; static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = …; static void __init exynos3_core_down_clock(void __iomem *reg_base) { … } static const struct samsung_cmu_info cmu_info __initconst = …; static void __init exynos3250_cmu_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); /* * CMU DMC */ #define BPLL_LOCK … #define BPLL_CON0 … #define BPLL_CON1 … #define BPLL_CON2 … #define SRC_DMC … #define DIV_DMC1 … #define GATE_BUS_DMC0 … #define GATE_BUS_DMC1 … #define GATE_BUS_DMC2 … #define GATE_BUS_DMC3 … #define GATE_SCLK_DMC … #define GATE_IP_DMC0 … #define GATE_IP_DMC1 … #define EPLL_LOCK … #define EPLL_CON0 … #define EPLL_CON1 … #define EPLL_CON2 … #define SRC_EPLL … static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = …; PNAME(mout_epll_p) = …; PNAME(mout_bpll_p) = …; PNAME(mout_mpll_mif_p) = …; PNAME(mout_dphy_p) = …; static const struct samsung_mux_clock dmc_mux_clks[] __initconst = …; static const struct samsung_div_clock dmc_div_clks[] __initconst = …; static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = …; static const struct samsung_cmu_info dmc_cmu_info __initconst = …; static void __init exynos3250_cmu_dmc_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", exynos3250_cmu_dmc_init); /* * CMU ISP */ #define DIV_ISP0 … #define DIV_ISP1 … #define GATE_IP_ISP0 … #define GATE_IP_ISP1 … #define GATE_SCLK_ISP … static const struct samsung_div_clock isp_div_clks[] __initconst = …; static const struct samsung_gate_clock isp_gate_clks[] __initconst = …; static const struct samsung_cmu_info isp_cmu_info __initconst = …; static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) { … } static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = …; static struct platform_driver exynos3250_cmu_isp_driver __initdata = …; static int __init exynos3250_cmu_platform_init(void) { … } subsys_initcall(exynos3250_cmu_platform_init);
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