// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Thomas Abraham <[email protected]> * * Copyright (c) 2015 Samsung Electronics Co., Ltd. * Bartlomiej Zolnierkiewicz <[email protected]> * * This file contains the utility function to register CPU clock for Samsung * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a * group of CPUs. The CPU clock is typically derived from a hierarchy of clock * blocks which includes mux and divider blocks. There are a number of other * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI * clock for CPU domain. The rates of these auxiliary clocks are related to the * CPU clock rate and this relation is usually specified in the hardware manual * of the SoC or supplied after the SoC characterization. * * The below implementation of the CPU clock allows the rate changes of the CPU * clock and the corresponding rate changes of the auxiliary clocks of the CPU * domain. The platform clock driver provides a clock register configuration * for each configurable rate which is then used to program the clock hardware * registers to achieve a fast coordinated rate change for all the CPU domain * clocks. * * On a rate change request for the CPU clock, the rate change is propagated * up to the PLL supplying the clock to the CPU domain clock blocks. While the * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an * alternate clock source. If required, the alternate clock source is divided * down in order to keep the output clock rate within the previous OPP limits. */ #include <linux/delay.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include "clk.h" #include "clk-cpu.h" struct exynos_cpuclk; exynos_rate_change_fn_t; /** * struct exynos_cpuclk_regs - Register offsets for CPU related clocks * @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent) * @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status) * @div_cpu0: offset of CPU DIV0 register (for modifying divider values) * @div_cpu1: offset of CPU DIV1 register (for modifying divider values) * @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status) * @div_stat_cpu1: offset of CPU DIV1_STAT register (for checking DIV status) * @mux: offset of MUX register for choosing CPU clock source * @divs: offsets of DIV registers (ACLK, ATCLK, PCLKDBG and PERIPHCLK) */ struct exynos_cpuclk_regs { … }; /** * struct exynos_cpuclk_chip - Chip specific data for CPU clock * @regs: register offsets for CPU related clocks * @pre_rate_cb: callback to run before CPU clock rate change * @post_rate_cb: callback to run after CPU clock rate change */ struct exynos_cpuclk_chip { … }; /** * struct exynos_cpuclk - information about clock supplied to a CPU core * @hw: handle between CCF and CPU clock * @alt_parent: alternate parent clock to use when switching the speed * of the primary parent clock * @base: start address of the CPU clock registers block * @lock: cpu clock domain register access lock * @cfg: cpu clock rate configuration data * @num_cfgs: number of array elements in @cfg array * @clk_nb: clock notifier registered for changes in clock speed of the * primary parent clock * @flags: configuration flags for the CPU clock * @chip: chip-specific data for the CPU clock * * This structure holds information required for programming the CPU clock for * various clock speeds. */ struct exynos_cpuclk { … }; /* ---- Common code --------------------------------------------------------- */ /* Divider stabilization time, msec */ #define MAX_STAB_TIME … #define MAX_DIV … #define DIV_MASK … #define DIV_MASK_ALL … #define MUX_MASK … /* * Helper function to wait until divider(s) have stabilized after the divider * value has changed. */ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) { … } /* * Helper function to wait until mux has stabilized after the mux selection * value was changed. */ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, unsigned long mask, unsigned long mux_value) { … } /* * Helper function to set the 'safe' dividers for the CPU clock. The parameters * div and mask contain the divider value and the register bit mask of the * dividers to be programmed. */ static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div, unsigned long mask) { … } /* ---- Exynos 3/4/5 -------------------------------------------------------- */ #define E4210_DIV0_RATIO0_MASK … #define E4210_DIV1_HPM_MASK … #define E4210_DIV1_COPY_MASK … #define E4210_MUX_HPM_MASK … #define E4210_DIV0_ATB_SHIFT … #define E4210_DIV0_ATB_MASK … static const struct exynos_cpuclk_regs e4210_cpuclk_regs = …; /* handler for pre-rate change notification from parent clock */ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* handler for post-rate change notification from parent clock */ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* ---- Exynos5433 ---------------------------------------------------------- */ static const struct exynos_cpuclk_regs e5433_cpuclk_regs = …; /* handler for pre-rate change notification from parent clock */ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* handler for post-rate change notification from parent clock */ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* ---- Exynos850 ----------------------------------------------------------- */ #define E850_DIV_RATIO_MASK … #define E850_BUSY_MASK … /* Max time for divider or mux to stabilize, usec */ #define E850_DIV_MUX_STAB_TIME … /* OSCCLK clock rate, Hz */ #define E850_OSCCLK … static const struct exynos_cpuclk_regs e850cl0_cpuclk_regs = …; static const struct exynos_cpuclk_regs e850cl1_cpuclk_regs = …; /* * Set alternate parent rate to "rate" value or less. * * rate: Desired alt_parent rate, or 0 for max alt_parent rate * * Exynos850 doesn't have CPU clock divider in CMU_CPUCLx block (CMUREF divider * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used * instead to adjust alternate parent speed. * * It's possible to use clk_set_max_rate() instead of this function, but it * would set overly pessimistic rate values to alternate parent. */ static int exynos850_alt_parent_set_max_rate(const struct clk_hw *alt_parent, unsigned long rate) { … } /* Handler for pre-rate change notification from parent clock */ static int exynos850_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* Handler for post-rate change notification from parent clock */ static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk) { … } /* -------------------------------------------------------------------------- */ /* Common round rate callback usable for all types of CPU clocks */ static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { … } /* Common recalc rate callback usable for all types of CPU clocks */ static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops exynos_cpuclk_clk_ops = …; /* * This notifier function is called for the pre-rate and post-rate change * notifications of the parent clock of cpuclk. */ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data) { … } static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = …; /* helper function to register a CPU clock */ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, const struct samsung_cpu_clock *clk_data) { … } void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx, const struct samsung_cpu_clock *list, unsigned int nr_clk) { … }
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