/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Rahul Sharma <[email protected]> * * Common Clock Framework support for Exynos5260 SoC. */ #ifndef __CLK_EXYNOS5260_H #define __CLK_EXYNOS5260_H /* *Registers for CMU_AUD */ #define MUX_SEL_AUD … #define MUX_ENABLE_AUD … #define MUX_STAT_AUD … #define MUX_IGNORE_AUD … #define DIV_AUD0 … #define DIV_AUD1 … #define DIV_STAT_AUD0 … #define DIV_STAT_AUD1 … #define EN_ACLK_AUD … #define EN_PCLK_AUD … #define EN_SCLK_AUD … #define EN_IP_AUD … /* *Registers for CMU_DISP */ #define MUX_SEL_DISP0 … #define MUX_SEL_DISP1 … #define MUX_SEL_DISP2 … #define MUX_SEL_DISP3 … #define MUX_SEL_DISP4 … #define MUX_ENABLE_DISP0 … #define MUX_ENABLE_DISP1 … #define MUX_ENABLE_DISP2 … #define MUX_ENABLE_DISP3 … #define MUX_ENABLE_DISP4 … #define MUX_STAT_DISP0 … #define MUX_STAT_DISP1 … #define MUX_STAT_DISP2 … #define MUX_STAT_DISP3 … #define MUX_STAT_DISP4 … #define MUX_IGNORE_DISP0 … #define MUX_IGNORE_DISP1 … #define MUX_IGNORE_DISP2 … #define MUX_IGNORE_DISP3 … #define MUX_IGNORE_DISP4 … #define DIV_DISP … #define DIV_STAT_DISP … #define EN_ACLK_DISP … #define EN_PCLK_DISP … #define EN_SCLK_DISP0 … #define EN_SCLK_DISP1 … #define EN_IP_DISP … #define EN_IP_DISP_BUS … /* *Registers for CMU_EGL */ #define EGL_PLL_LOCK … #define EGL_DPLL_LOCK … #define EGL_PLL_CON0 … #define EGL_PLL_CON1 … #define EGL_PLL_FREQ_DET … #define EGL_DPLL_CON0 … #define EGL_DPLL_CON1 … #define EGL_DPLL_FREQ_DET … #define MUX_SEL_EGL … #define MUX_ENABLE_EGL … #define MUX_STAT_EGL … #define DIV_EGL … #define DIV_EGL_PLL_FDET … #define DIV_STAT_EGL … #define DIV_STAT_EGL_PLL_FDET … #define EN_ACLK_EGL … #define EN_PCLK_EGL … #define EN_SCLK_EGL … #define EN_IP_EGL … #define CLKOUT_CMU_EGL … #define CLKOUT_CMU_EGL_DIV_STAT … #define ARMCLK_STOPCTRL … #define EAGLE_EMA_CTRL … #define EAGLE_EMA_STATUS … #define PWR_CTRL … #define PWR_CTRL2 … #define CLKSTOP_CTRL … #define INTR_SPREAD_EN … #define INTR_SPREAD_USE_STANDBYWFI … #define INTR_SPREAD_BLOCKING_DURATION … #define CMU_EGL_SPARE0 … #define CMU_EGL_SPARE1 … #define CMU_EGL_SPARE2 … #define CMU_EGL_SPARE3 … #define CMU_EGL_SPARE4 … /* *Registers for CMU_FSYS */ #define MUX_SEL_FSYS0 … #define MUX_SEL_FSYS1 … #define MUX_ENABLE_FSYS0 … #define MUX_ENABLE_FSYS1 … #define MUX_STAT_FSYS0 … #define MUX_STAT_FSYS1 … #define MUX_IGNORE_FSYS0 … #define MUX_IGNORE_FSYS1 … #define EN_ACLK_FSYS … #define EN_ACLK_FSYS_SECURE_RTIC … #define EN_ACLK_FSYS_SECURE_SMMU_RTIC … #define EN_PCLK_FSYS … #define EN_SCLK_FSYS … #define EN_IP_FSYS … #define EN_IP_FSYS_SECURE_RTIC … #define EN_IP_FSYS_SECURE_SMMU_RTIC … /* *Registers for CMU_G2D */ #define MUX_SEL_G2D … #define MUX_ENABLE_G2D … #define MUX_STAT_G2D … #define DIV_G2D … #define DIV_STAT_G2D … #define EN_ACLK_G2D … #define EN_ACLK_G2D_SECURE_SSS … #define EN_ACLK_G2D_SECURE_SLIM_SSS … #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS … #define EN_ACLK_G2D_SECURE_SMMU_SSS … #define EN_ACLK_G2D_SECURE_SMMU_MDMA … #define EN_ACLK_G2D_SECURE_SMMU_G2D … #define EN_PCLK_G2D … #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS … #define EN_PCLK_G2D_SECURE_SMMU_SSS … #define EN_PCLK_G2D_SECURE_SMMU_MDMA … #define EN_PCLK_G2D_SECURE_SMMU_G2D … #define EN_IP_G2D … #define EN_IP_G2D_SECURE_SSS … #define EN_IP_G2D_SECURE_SLIM_SSS … #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS … #define EN_IP_G2D_SECURE_SMMU_SSS … #define EN_IP_G2D_SECURE_SMMU_MDMA … #define EN_IP_G2D_SECURE_SMMU_G2D … /* *Registers for CMU_G3D */ #define G3D_PLL_LOCK … #define G3D_PLL_CON0 … #define G3D_PLL_CON1 … #define G3D_PLL_FDET … #define MUX_SEL_G3D … #define MUX_EN_G3D … #define MUX_STAT_G3D … #define MUX_IGNORE_G3D … #define DIV_G3D … #define DIV_G3D_PLL_FDET … #define DIV_STAT_G3D … #define DIV_STAT_G3D_PLL_FDET … #define EN_ACLK_G3D … #define EN_PCLK_G3D … #define EN_SCLK_G3D … #define EN_IP_G3D … #define CLKOUT_CMU_G3D … #define CLKOUT_CMU_G3D_DIV_STAT … #define G3DCLK_STOPCTRL … #define G3D_EMA_CTRL … #define G3D_EMA_STATUS … /* *Registers for CMU_GSCL */ #define MUX_SEL_GSCL … #define MUX_EN_GSCL … #define MUX_STAT_GSCL … #define MUX_IGNORE_GSCL … #define DIV_GSCL … #define DIV_STAT_GSCL … #define EN_ACLK_GSCL … #define EN_ACLK_GSCL_FIMC … #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 … #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 … #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 … #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 … #define EN_PCLK_GSCL … #define EN_PCLK_GSCL_FIMC … #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 … #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 … #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 … #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 … #define EN_SCLK_GSCL … #define EN_SCLK_GSCL_FIMC … #define EN_IP_GSCL … #define EN_IP_GSCL_FIMC … #define EN_IP_GSCL_SECURE_SMMU_GSCL0 … #define EN_IP_GSCL_SECURE_SMMU_GSCL1 … #define EN_IP_GSCL_SECURE_SMMU_MSCL0 … #define EN_IP_GSCL_SECURE_SMMU_MSCL1 … /* *Registers for CMU_ISP */ #define MUX_SEL_ISP0 … #define MUX_SEL_ISP1 … #define MUX_ENABLE_ISP0 … #define MUX_ENABLE_ISP1 … #define MUX_STAT_ISP0 … #define MUX_STAT_ISP1 … #define MUX_IGNORE_ISP0 … #define MUX_IGNORE_ISP1 … #define DIV_ISP … #define DIV_STAT_ISP … #define EN_ACLK_ISP0 … #define EN_ACLK_ISP1 … #define EN_PCLK_ISP0 … #define EN_PCLK_ISP1 … #define EN_SCLK_ISP … #define EN_IP_ISP0 … #define EN_IP_ISP1 … /* *Registers for CMU_KFC */ #define KFC_PLL_LOCK … #define KFC_PLL_CON0 … #define KFC_PLL_CON1 … #define KFC_PLL_FDET … #define MUX_SEL_KFC0 … #define MUX_SEL_KFC2 … #define MUX_ENABLE_KFC0 … #define MUX_ENABLE_KFC2 … #define MUX_STAT_KFC0 … #define MUX_STAT_KFC2 … #define DIV_KFC … #define DIV_KFC_PLL_FDET … #define DIV_STAT_KFC … #define DIV_STAT_KFC_PLL_FDET … #define EN_ACLK_KFC … #define EN_PCLK_KFC … #define EN_SCLK_KFC … #define EN_IP_KFC … #define CLKOUT_CMU_KFC … #define CLKOUT_CMU_KFC_DIV_STAT … #define ARMCLK_STOPCTRL_KFC … #define ARM_EMA_CTRL … #define ARM_EMA_STATUS … #define PWR_CTRL_KFC … #define PWR_CTRL2_KFC … #define CLKSTOP_CTRL_KFC … #define INTR_SPREAD_ENABLE_KFC … #define INTR_SPREAD_USE_STANDBYWFI_KFC … #define INTR_SPREAD_BLOCKING_DURATION_KFC … #define CMU_KFC_SPARE0 … #define CMU_KFC_SPARE1 … #define CMU_KFC_SPARE2 … #define CMU_KFC_SPARE3 … #define CMU_KFC_SPARE4 … /* *Registers for CMU_MFC */ #define MUX_SEL_MFC … #define MUX_ENABLE_MFC … #define MUX_STAT_MFC … #define DIV_MFC … #define DIV_STAT_MFC … #define EN_ACLK_MFC … #define EN_ACLK_SECURE_SMMU2_MFC … #define EN_PCLK_MFC … #define EN_PCLK_SECURE_SMMU2_MFC … #define EN_IP_MFC … #define EN_IP_MFC_SECURE_SMMU2_MFC … /* *Registers for CMU_MIF */ #define MEM_PLL_LOCK … #define BUS_PLL_LOCK … #define MEDIA_PLL_LOCK … #define MEM_PLL_CON0 … #define MEM_PLL_CON1 … #define MEM_PLL_FDET … #define BUS_PLL_CON0 … #define BUS_PLL_CON1 … #define BUS_PLL_FDET … #define MEDIA_PLL_CON0 … #define MEDIA_PLL_CON1 … #define MEDIA_PLL_FDET … #define MUX_SEL_MIF … #define MUX_ENABLE_MIF … #define MUX_STAT_MIF … #define MUX_IGNORE_MIF … #define DIV_MIF … #define DIV_MIF_PLL_FDET … #define DIV_STAT_MIF … #define DIV_STAT_MIF_PLL_FDET … #define EN_ACLK_MIF … #define EN_ACLK_MIF_SECURE_DREX1_TZ … #define EN_ACLK_MIF_SECURE_DREX0_TZ … #define EN_ACLK_MIF_SECURE_INTMEM … #define EN_PCLK_MIF … #define EN_PCLK_MIF_SECURE_MONOCNT … #define EN_PCLK_MIF_SECURE_RTC_APBIF … #define EN_PCLK_MIF_SECURE_DREX1_TZ … #define EN_PCLK_MIF_SECURE_DREX0_TZ … #define EN_SCLK_MIF … #define EN_IP_MIF … #define EN_IP_MIF_SECURE_MONOCNT … #define EN_IP_MIF_SECURE_RTC_APBIF … #define EN_IP_MIF_SECURE_DREX1_TZ … #define EN_IP_MIF_SECURE_DREX0_TZ … #define EN_IP_MIF_SECURE_INTEMEM … #define CLKOUT_CMU_MIF_DIV_STAT … #define DREX_FREQ_CTRL … #define PAUSE … #define DDRPHY_LOCK_CTRL … #define CLKOUT_CMU_MIF … /* *Registers for CMU_PERI */ #define MUX_SEL_PERI … #define MUX_SEL_PERI1 … #define MUX_ENABLE_PERI … #define MUX_ENABLE_PERI1 … #define MUX_STAT_PERI … #define MUX_STAT_PERI1 … #define MUX_IGNORE_PERI … #define MUX_IGNORE_PERI1 … #define DIV_PERI … #define DIV_STAT_PERI … #define EN_PCLK_PERI0 … #define EN_PCLK_PERI1 … #define EN_PCLK_PERI2 … #define EN_PCLK_PERI3 … #define EN_PCLK_PERI_SECURE_CHIPID … #define EN_PCLK_PERI_SECURE_PROVKEY0 … #define EN_PCLK_PERI_SECURE_PROVKEY1 … #define EN_PCLK_PERI_SECURE_SECKEY … #define EN_PCLK_PERI_SECURE_ANTIRBKCNT … #define EN_PCLK_PERI_SECURE_TOP_RTC … #define EN_PCLK_PERI_SECURE_TZPC … #define EN_SCLK_PERI … #define EN_SCLK_PERI_SECURE_TOP_RTC … #define EN_IP_PERI0 … #define EN_IP_PERI1 … #define EN_IP_PERI2 … #define EN_IP_PERI_SECURE_CHIPID … #define EN_IP_PERI_SECURE_PROVKEY0 … #define EN_IP_PERI_SECURE_PROVKEY1 … #define EN_IP_PERI_SECURE_SECKEY … #define EN_IP_PERI_SECURE_ANTIRBKCNT … #define EN_IP_PERI_SECURE_TOP_RTC … #define EN_IP_PERI_SECURE_TZPC … /* *Registers for CMU_TOP */ #define DISP_PLL_LOCK … #define AUD_PLL_LOCK … #define DISP_PLL_CON0 … #define DISP_PLL_CON1 … #define DISP_PLL_FDET … #define AUD_PLL_CON0 … #define AUD_PLL_CON1 … #define AUD_PLL_CON2 … #define AUD_PLL_FDET … #define MUX_SEL_TOP_PLL0 … #define MUX_SEL_TOP_MFC … #define MUX_SEL_TOP_G2D … #define MUX_SEL_TOP_GSCL … #define MUX_SEL_TOP_ISP10 … #define MUX_SEL_TOP_ISP11 … #define MUX_SEL_TOP_DISP0 … #define MUX_SEL_TOP_DISP1 … #define MUX_SEL_TOP_BUS … #define MUX_SEL_TOP_PERI0 … #define MUX_SEL_TOP_PERI1 … #define MUX_SEL_TOP_FSYS … #define MUX_ENABLE_TOP_PLL0 … #define MUX_ENABLE_TOP_MFC … #define MUX_ENABLE_TOP_G2D … #define MUX_ENABLE_TOP_GSCL … #define MUX_ENABLE_TOP_ISP10 … #define MUX_ENABLE_TOP_ISP11 … #define MUX_ENABLE_TOP_DISP0 … #define MUX_ENABLE_TOP_DISP1 … #define MUX_ENABLE_TOP_BUS … #define MUX_ENABLE_TOP_PERI0 … #define MUX_ENABLE_TOP_PERI1 … #define MUX_ENABLE_TOP_FSYS … #define MUX_STAT_TOP_PLL0 … #define MUX_STAT_TOP_MFC … #define MUX_STAT_TOP_G2D … #define MUX_STAT_TOP_GSCL … #define MUX_STAT_TOP_ISP10 … #define MUX_STAT_TOP_ISP11 … #define MUX_STAT_TOP_DISP0 … #define MUX_STAT_TOP_DISP1 … #define MUX_STAT_TOP_BUS … #define MUX_STAT_TOP_PERI0 … #define MUX_STAT_TOP_PERI1 … #define MUX_STAT_TOP_FSYS … #define MUX_IGNORE_TOP_PLL0 … #define MUX_IGNORE_TOP_MFC … #define MUX_IGNORE_TOP_G2D … #define MUX_IGNORE_TOP_GSCL … #define MUX_IGNORE_TOP_ISP10 … #define MUX_IGNORE_TOP_ISP11 … #define MUX_IGNORE_TOP_DISP0 … #define MUX_IGNORE_TOP_DISP1 … #define MUX_IGNORE_TOP_BUS … #define MUX_IGNORE_TOP_PERI0 … #define MUX_IGNORE_TOP_PERI1 … #define MUX_IGNORE_TOP_FSYS … #define DIV_TOP_G2D_MFC … #define DIV_TOP_GSCL_ISP0 … #define DIV_TOP_ISP10 … #define DIV_TOP_ISP11 … #define DIV_TOP_DISP … #define DIV_TOP_BUS … #define DIV_TOP_PERI0 … #define DIV_TOP_PERI1 … #define DIV_TOP_PERI2 … #define DIV_TOP_FSYS0 … #define DIV_TOP_FSYS1 … #define DIV_TOP_HPM … #define DIV_TOP_PLL_FDET … #define DIV_STAT_TOP_G2D_MFC … #define DIV_STAT_TOP_GSCL_ISP0 … #define DIV_STAT_TOP_ISP10 … #define DIV_STAT_TOP_ISP11 … #define DIV_STAT_TOP_DISP … #define DIV_STAT_TOP_BUS … #define DIV_STAT_TOP_PERI0 … #define DIV_STAT_TOP_PERI1 … #define DIV_STAT_TOP_PERI2 … #define DIV_STAT_TOP_FSYS0 … #define DIV_STAT_TOP_FSYS1 … #define DIV_STAT_TOP_HPM … #define DIV_STAT_TOP_PLL_FDET … #define EN_ACLK_TOP … #define EN_SCLK_TOP … #define EN_IP_TOP … #define CLKOUT_CMU_TOP … #define CLKOUT_CMU_TOP_DIV_STAT … #endif /*__CLK_EXYNOS5260_H */
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