/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Chanwoo Choi <[email protected]> */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H #define _DT_BINDINGS_CLOCK_EXYNOS5433_H /* CMU_TOP */ #define CLK_FOUT_ISP_PLL … #define CLK_FOUT_AUD_PLL … #define CLK_MOUT_AUD_PLL … #define CLK_MOUT_ISP_PLL … #define CLK_MOUT_AUD_PLL_USER_T … #define CLK_MOUT_MPHY_PLL_USER … #define CLK_MOUT_MFC_PLL_USER … #define CLK_MOUT_BUS_PLL_USER … #define CLK_MOUT_ACLK_HEVC_400 … #define CLK_MOUT_ACLK_CAM1_333 … #define CLK_MOUT_ACLK_CAM1_552_B … #define CLK_MOUT_ACLK_CAM1_552_A … #define CLK_MOUT_ACLK_ISP_DIS_400 … #define CLK_MOUT_ACLK_ISP_400 … #define CLK_MOUT_ACLK_BUS0_400 … #define CLK_MOUT_ACLK_MSCL_400_B … #define CLK_MOUT_ACLK_MSCL_400_A … #define CLK_MOUT_ACLK_GSCL_333 … #define CLK_MOUT_ACLK_G2D_400_B … #define CLK_MOUT_ACLK_G2D_400_A … #define CLK_MOUT_SCLK_JPEG_C … #define CLK_MOUT_SCLK_JPEG_B … #define CLK_MOUT_SCLK_JPEG_A … #define CLK_MOUT_SCLK_MMC2_B … #define CLK_MOUT_SCLK_MMC2_A … #define CLK_MOUT_SCLK_MMC1_B … #define CLK_MOUT_SCLK_MMC1_A … #define CLK_MOUT_SCLK_MMC0_D … #define CLK_MOUT_SCLK_MMC0_C … #define CLK_MOUT_SCLK_MMC0_B … #define CLK_MOUT_SCLK_MMC0_A … #define CLK_MOUT_SCLK_SPI4 … #define CLK_MOUT_SCLK_SPI3 … #define CLK_MOUT_SCLK_UART2 … #define CLK_MOUT_SCLK_UART1 … #define CLK_MOUT_SCLK_UART0 … #define CLK_MOUT_SCLK_SPI2 … #define CLK_MOUT_SCLK_SPI1 … #define CLK_MOUT_SCLK_SPI0 … #define CLK_MOUT_ACLK_MFC_400_C … #define CLK_MOUT_ACLK_MFC_400_B … #define CLK_MOUT_ACLK_MFC_400_A … #define CLK_MOUT_SCLK_ISP_SENSOR2 … #define CLK_MOUT_SCLK_ISP_SENSOR1 … #define CLK_MOUT_SCLK_ISP_SENSOR0 … #define CLK_MOUT_SCLK_ISP_UART … #define CLK_MOUT_SCLK_ISP_SPI1 … #define CLK_MOUT_SCLK_ISP_SPI0 … #define CLK_MOUT_SCLK_PCIE_100 … #define CLK_MOUT_SCLK_UFSUNIPRO … #define CLK_MOUT_SCLK_USBHOST30 … #define CLK_MOUT_SCLK_USBDRD30 … #define CLK_MOUT_SCLK_SLIMBUS … #define CLK_MOUT_SCLK_SPDIF … #define CLK_MOUT_SCLK_AUDIO1 … #define CLK_MOUT_SCLK_AUDIO0 … #define CLK_MOUT_SCLK_HDMI_SPDIF … #define CLK_DIV_ACLK_FSYS_200 … #define CLK_DIV_ACLK_IMEM_SSSX_266 … #define CLK_DIV_ACLK_IMEM_200 … #define CLK_DIV_ACLK_IMEM_266 … #define CLK_DIV_ACLK_PERIC_66_B … #define CLK_DIV_ACLK_PERIC_66_A … #define CLK_DIV_ACLK_PERIS_66_B … #define CLK_DIV_ACLK_PERIS_66_A … #define CLK_DIV_SCLK_MMC1_B … #define CLK_DIV_SCLK_MMC1_A … #define CLK_DIV_SCLK_MMC0_B … #define CLK_DIV_SCLK_MMC0_A … #define CLK_DIV_SCLK_MMC2_B … #define CLK_DIV_SCLK_MMC2_A … #define CLK_DIV_SCLK_SPI1_B … #define CLK_DIV_SCLK_SPI1_A … #define CLK_DIV_SCLK_SPI0_B … #define CLK_DIV_SCLK_SPI0_A … #define CLK_DIV_SCLK_SPI2_B … #define CLK_DIV_SCLK_SPI2_A … #define CLK_DIV_SCLK_UART2 … #define CLK_DIV_SCLK_UART1 … #define CLK_DIV_SCLK_UART0 … #define CLK_DIV_SCLK_SPI4_B … #define CLK_DIV_SCLK_SPI4_A … #define CLK_DIV_SCLK_SPI3_B … #define CLK_DIV_SCLK_SPI3_A … #define CLK_DIV_SCLK_I2S1 … #define CLK_DIV_SCLK_PCM1 … #define CLK_DIV_SCLK_AUDIO1 … #define CLK_DIV_SCLK_AUDIO0 … #define CLK_DIV_ACLK_GSCL_111 … #define CLK_DIV_ACLK_GSCL_333 … #define CLK_DIV_ACLK_HEVC_400 … #define CLK_DIV_ACLK_MFC_400 … #define CLK_DIV_ACLK_G2D_266 … #define CLK_DIV_ACLK_G2D_400 … #define CLK_DIV_ACLK_G3D_400 … #define CLK_DIV_ACLK_BUS0_400 … #define CLK_DIV_ACLK_BUS1_400 … #define CLK_DIV_SCLK_PCIE_100 … #define CLK_DIV_SCLK_USBHOST30 … #define CLK_DIV_SCLK_UFSUNIPRO … #define CLK_DIV_SCLK_USBDRD30 … #define CLK_DIV_SCLK_JPEG … #define CLK_DIV_ACLK_MSCL_400 … #define CLK_DIV_ACLK_ISP_DIS_400 … #define CLK_DIV_ACLK_ISP_400 … #define CLK_DIV_ACLK_CAM0_333 … #define CLK_DIV_ACLK_CAM0_400 … #define CLK_DIV_ACLK_CAM0_552 … #define CLK_DIV_ACLK_CAM1_333 … #define CLK_DIV_ACLK_CAM1_400 … #define CLK_DIV_ACLK_CAM1_552 … #define CLK_DIV_SCLK_ISP_UART … #define CLK_DIV_SCLK_ISP_SPI1_B … #define CLK_DIV_SCLK_ISP_SPI1_A … #define CLK_DIV_SCLK_ISP_SPI0_B … #define CLK_DIV_SCLK_ISP_SPI0_A … #define CLK_DIV_SCLK_ISP_SENSOR2_B … #define CLK_DIV_SCLK_ISP_SENSOR2_A … #define CLK_DIV_SCLK_ISP_SENSOR1_B … #define CLK_DIV_SCLK_ISP_SENSOR1_A … #define CLK_DIV_SCLK_ISP_SENSOR0_B … #define CLK_DIV_SCLK_ISP_SENSOR0_A … #define CLK_ACLK_PERIC_66 … #define CLK_ACLK_PERIS_66 … #define CLK_ACLK_FSYS_200 … #define CLK_SCLK_MMC2_FSYS … #define CLK_SCLK_MMC1_FSYS … #define CLK_SCLK_MMC0_FSYS … #define CLK_SCLK_SPI4_PERIC … #define CLK_SCLK_SPI3_PERIC … #define CLK_SCLK_UART2_PERIC … #define CLK_SCLK_UART1_PERIC … #define CLK_SCLK_UART0_PERIC … #define CLK_SCLK_SPI2_PERIC … #define CLK_SCLK_SPI1_PERIC … #define CLK_SCLK_SPI0_PERIC … #define CLK_SCLK_SPDIF_PERIC … #define CLK_SCLK_I2S1_PERIC … #define CLK_SCLK_PCM1_PERIC … #define CLK_SCLK_SLIMBUS … #define CLK_SCLK_AUDIO1 … #define CLK_SCLK_AUDIO0 … #define CLK_ACLK_G2D_266 … #define CLK_ACLK_G2D_400 … #define CLK_ACLK_G3D_400 … #define CLK_ACLK_IMEM_SSSX_266 … #define CLK_ACLK_BUS0_400 … #define CLK_ACLK_BUS1_400 … #define CLK_ACLK_IMEM_200 … #define CLK_ACLK_IMEM_266 … #define CLK_SCLK_PCIE_100_FSYS … #define CLK_SCLK_UFSUNIPRO_FSYS … #define CLK_SCLK_USBHOST30_FSYS … #define CLK_SCLK_USBDRD30_FSYS … #define CLK_ACLK_GSCL_111 … #define CLK_ACLK_GSCL_333 … #define CLK_SCLK_JPEG_MSCL … #define CLK_ACLK_MSCL_400 … #define CLK_ACLK_MFC_400 … #define CLK_ACLK_HEVC_400 … #define CLK_ACLK_ISP_DIS_400 … #define CLK_ACLK_ISP_400 … #define CLK_ACLK_CAM0_333 … #define CLK_ACLK_CAM0_400 … #define CLK_ACLK_CAM0_552 … #define CLK_ACLK_CAM1_333 … #define CLK_ACLK_CAM1_400 … #define CLK_ACLK_CAM1_552 … #define CLK_SCLK_ISP_SENSOR2 … #define CLK_SCLK_ISP_SENSOR1 … #define CLK_SCLK_ISP_SENSOR0 … #define CLK_SCLK_ISP_MCTADC_CAM1 … #define CLK_SCLK_ISP_UART_CAM1 … #define CLK_SCLK_ISP_SPI1_CAM1 … #define CLK_SCLK_ISP_SPI0_CAM1 … #define CLK_SCLK_HDMI_SPDIF_DISP … /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL … #define CLK_MOUT_MPHY_PLL … #define CLK_DIV_SCLK_MPHY … #define CLK_SCLK_MPHY_PLL … #define CLK_SCLK_UFS_MPHY … /* CMU_MIF */ #define CLK_FOUT_MEM0_PLL … #define CLK_FOUT_MEM1_PLL … #define CLK_FOUT_BUS_PLL … #define CLK_FOUT_MFC_PLL … #define CLK_DOUT_MFC_PLL … #define CLK_DOUT_BUS_PLL … #define CLK_DOUT_MEM1_PLL … #define CLK_DOUT_MEM0_PLL … #define CLK_MOUT_MFC_PLL_DIV2 … #define CLK_MOUT_BUS_PLL_DIV2 … #define CLK_MOUT_MEM1_PLL_DIV2 … #define CLK_MOUT_MEM0_PLL_DIV2 … #define CLK_MOUT_MFC_PLL … #define CLK_MOUT_BUS_PLL … #define CLK_MOUT_MEM1_PLL … #define CLK_MOUT_MEM0_PLL … #define CLK_MOUT_CLK2X_PHY_C … #define CLK_MOUT_CLK2X_PHY_B … #define CLK_MOUT_CLK2X_PHY_A … #define CLK_MOUT_CLKM_PHY_C … #define CLK_MOUT_CLKM_PHY_B … #define CLK_MOUT_CLKM_PHY_A … #define CLK_MOUT_ACLK_MIFNM_200 … #define CLK_MOUT_ACLK_MIFNM_400 … #define CLK_MOUT_ACLK_DISP_333_B … #define CLK_MOUT_ACLK_DISP_333_A … #define CLK_MOUT_SCLK_DECON_VCLK_C … #define CLK_MOUT_SCLK_DECON_VCLK_B … #define CLK_MOUT_SCLK_DECON_VCLK_A … #define CLK_MOUT_SCLK_DECON_ECLK_C … #define CLK_MOUT_SCLK_DECON_ECLK_B … #define CLK_MOUT_SCLK_DECON_ECLK_A … #define CLK_MOUT_SCLK_DECON_TV_ECLK_C … #define CLK_MOUT_SCLK_DECON_TV_ECLK_B … #define CLK_MOUT_SCLK_DECON_TV_ECLK_A … #define CLK_MOUT_SCLK_DSD_C … #define CLK_MOUT_SCLK_DSD_B … #define CLK_MOUT_SCLK_DSD_A … #define CLK_MOUT_SCLK_DSIM0_C … #define CLK_MOUT_SCLK_DSIM0_B … #define CLK_MOUT_SCLK_DSIM0_A … #define CLK_MOUT_SCLK_DECON_TV_VCLK_C … #define CLK_MOUT_SCLK_DECON_TV_VCLK_B … #define CLK_MOUT_SCLK_DECON_TV_VCLK_A … #define CLK_MOUT_SCLK_DSIM1_C … #define CLK_MOUT_SCLK_DSIM1_B … #define CLK_MOUT_SCLK_DSIM1_A … #define CLK_DIV_SCLK_HPM_MIF … #define CLK_DIV_ACLK_DREX1 … #define CLK_DIV_ACLK_DREX0 … #define CLK_DIV_CLK2XPHY … #define CLK_DIV_ACLK_MIF_266 … #define CLK_DIV_ACLK_MIFND_133 … #define CLK_DIV_ACLK_MIF_133 … #define CLK_DIV_ACLK_MIFNM_200 … #define CLK_DIV_ACLK_MIF_200 … #define CLK_DIV_ACLK_MIF_400 … #define CLK_DIV_ACLK_BUS2_400 … #define CLK_DIV_ACLK_DISP_333 … #define CLK_DIV_ACLK_CPIF_200 … #define CLK_DIV_SCLK_DSIM1 … #define CLK_DIV_SCLK_DECON_TV_VCLK … #define CLK_DIV_SCLK_DSIM0 … #define CLK_DIV_SCLK_DSD … #define CLK_DIV_SCLK_DECON_TV_ECLK … #define CLK_DIV_SCLK_DECON_VCLK … #define CLK_DIV_SCLK_DECON_ECLK … #define CLK_DIV_MIF_PRE … #define CLK_CLK2X_PHY1 … #define CLK_CLK2X_PHY0 … #define CLK_CLKM_PHY1 … #define CLK_CLKM_PHY0 … #define CLK_RCLK_DREX1 … #define CLK_RCLK_DREX0 … #define CLK_ACLK_DREX1_TZ … #define CLK_ACLK_DREX0_TZ … #define CLK_ACLK_DREX1_PEREV … #define CLK_ACLK_DREX0_PEREV … #define CLK_ACLK_DREX1_MEMIF … #define CLK_ACLK_DREX0_MEMIF … #define CLK_ACLK_DREX1_SCH … #define CLK_ACLK_DREX0_SCH … #define CLK_ACLK_DREX1_BUSIF … #define CLK_ACLK_DREX0_BUSIF … #define CLK_ACLK_DREX1_BUSIF_RD … #define CLK_ACLK_DREX0_BUSIF_RD … #define CLK_ACLK_DREX1 … #define CLK_ACLK_DREX0 … #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX … #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF … #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF … #define CLK_ACLK_ASYNCAXIS_MIF_IMEM … #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI … #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI … #define CLK_ACLK_ASYNCAXIS_CP1 … #define CLK_ACLK_ASYNCAXIM_CP1 … #define CLK_ACLK_ASYNCAXIS_CP0 … #define CLK_ACLK_ASYNCAXIM_CP0 … #define CLK_ACLK_ASYNCAXIS_DREX1_3 … #define CLK_ACLK_ASYNCAXIM_DREX1_3 … #define CLK_ACLK_ASYNCAXIS_DREX1_1 … #define CLK_ACLK_ASYNCAXIM_DREX1_1 … #define CLK_ACLK_ASYNCAXIS_DREX1_0 … #define CLK_ACLK_ASYNCAXIM_DREX1_0 … #define CLK_ACLK_ASYNCAXIS_DREX0_3 … #define CLK_ACLK_ASYNCAXIM_DREX0_3 … #define CLK_ACLK_ASYNCAXIS_DREX0_1 … #define CLK_ACLK_ASYNCAXIM_DREX0_1 … #define CLK_ACLK_ASYNCAXIS_DREX0_0 … #define CLK_ACLK_ASYNCAXIM_DREX0_0 … #define CLK_ACLK_AHB2APB_MIF2P … #define CLK_ACLK_AHB2APB_MIF1P … #define CLK_ACLK_AHB2APB_MIF0P … #define CLK_ACLK_IXIU_CCI … #define CLK_ACLK_XIU_MIFSFRX … #define CLK_ACLK_MIFNP_133 … #define CLK_ACLK_MIFNM_200 … #define CLK_ACLK_MIFND_133 … #define CLK_ACLK_MIFND_400 … #define CLK_ACLK_CCI … #define CLK_ACLK_MIFND_266 … #define CLK_ACLK_PPMU_DREX1S3 … #define CLK_ACLK_PPMU_DREX1S1 … #define CLK_ACLK_PPMU_DREX1S0 … #define CLK_ACLK_PPMU_DREX0S3 … #define CLK_ACLK_PPMU_DREX0S1 … #define CLK_ACLK_PPMU_DREX0S0 … #define CLK_ACLK_BTS_APOLLO … #define CLK_ACLK_BTS_ATLAS … #define CLK_ACLK_ACE_SEL_APOLL … #define CLK_ACLK_ACE_SEL_ATLAS … #define CLK_ACLK_AXIDS_CCI_MIFSFRX … #define CLK_ACLK_AXIUS_ATLAS_CCI … #define CLK_ACLK_AXISYNCDNS_CCI … #define CLK_ACLK_AXISYNCDN_CCI … #define CLK_ACLK_AXISYNCDN_NOC_D … #define CLK_ACLK_ASYNCACEM_APOLLO_CCI … #define CLK_ACLK_ASYNCACEM_ATLAS_CCI … #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS … #define CLK_ACLK_BUS2_400 … #define CLK_ACLK_DISP_333 … #define CLK_ACLK_CPIF_200 … #define CLK_PCLK_PPMU_DREX1S3 … #define CLK_PCLK_PPMU_DREX1S1 … #define CLK_PCLK_PPMU_DREX1S0 … #define CLK_PCLK_PPMU_DREX0S3 … #define CLK_PCLK_PPMU_DREX0S1 … #define CLK_PCLK_PPMU_DREX0S0 … #define CLK_PCLK_BTS_APOLLO … #define CLK_PCLK_BTS_ATLAS … #define CLK_PCLK_ASYNCAXI_NOC_P_CCI … #define CLK_PCLK_ASYNCAXI_CP1 … #define CLK_PCLK_ASYNCAXI_CP0 … #define CLK_PCLK_ASYNCAXI_DREX1_3 … #define CLK_PCLK_ASYNCAXI_DREX1_1 … #define CLK_PCLK_ASYNCAXI_DREX1_0 … #define CLK_PCLK_ASYNCAXI_DREX0_3 … #define CLK_PCLK_ASYNCAXI_DREX0_1 … #define CLK_PCLK_ASYNCAXI_DREX0_0 … #define CLK_PCLK_MIFSRVND_133 … #define CLK_PCLK_PMU_MIF … #define CLK_PCLK_SYSREG_MIF … #define CLK_PCLK_GPIO_ALIVE … #define CLK_PCLK_ABB … #define CLK_PCLK_PMU_APBIF … #define CLK_PCLK_DDR_PHY1 … #define CLK_PCLK_DREX1 … #define CLK_PCLK_DDR_PHY0 … #define CLK_PCLK_DREX0 … #define CLK_PCLK_DREX0_TZ … #define CLK_PCLK_DREX1_TZ … #define CLK_PCLK_MONOTONIC_CNT … #define CLK_PCLK_RTC … #define CLK_SCLK_DSIM1_DISP … #define CLK_SCLK_DECON_TV_VCLK_DISP … #define CLK_SCLK_FREQ_DET_BUS_PLL … #define CLK_SCLK_FREQ_DET_MFC_PLL … #define CLK_SCLK_FREQ_DET_MEM0_PLL … #define CLK_SCLK_FREQ_DET_MEM1_PLL … #define CLK_SCLK_DSIM0_DISP … #define CLK_SCLK_DSD_DISP … #define CLK_SCLK_DECON_TV_ECLK_DISP … #define CLK_SCLK_DECON_VCLK_DISP … #define CLK_SCLK_DECON_ECLK_DISP … #define CLK_SCLK_HPM_MIF … #define CLK_SCLK_MFC_PLL … #define CLK_SCLK_BUS_PLL … #define CLK_SCLK_BUS_PLL_APOLLO … #define CLK_SCLK_BUS_PLL_ATLAS … /* CMU_PERIC */ #define CLK_PCLK_SPI2 … #define CLK_PCLK_SPI1 … #define CLK_PCLK_SPI0 … #define CLK_PCLK_UART2 … #define CLK_PCLK_UART1 … #define CLK_PCLK_UART0 … #define CLK_PCLK_HSI2C3 … #define CLK_PCLK_HSI2C2 … #define CLK_PCLK_HSI2C1 … #define CLK_PCLK_HSI2C0 … #define CLK_PCLK_I2C7 … #define CLK_PCLK_I2C6 … #define CLK_PCLK_I2C5 … #define CLK_PCLK_I2C4 … #define CLK_PCLK_I2C3 … #define CLK_PCLK_I2C2 … #define CLK_PCLK_I2C1 … #define CLK_PCLK_I2C0 … #define CLK_PCLK_SPI4 … #define CLK_PCLK_SPI3 … #define CLK_PCLK_HSI2C11 … #define CLK_PCLK_HSI2C10 … #define CLK_PCLK_HSI2C9 … #define CLK_PCLK_HSI2C8 … #define CLK_PCLK_HSI2C7 … #define CLK_PCLK_HSI2C6 … #define CLK_PCLK_HSI2C5 … #define CLK_PCLK_HSI2C4 … #define CLK_SCLK_SPI4 … #define CLK_SCLK_SPI3 … #define CLK_SCLK_SPI2 … #define CLK_SCLK_SPI1 … #define CLK_SCLK_SPI0 … #define CLK_SCLK_UART2 … #define CLK_SCLK_UART1 … #define CLK_SCLK_UART0 … #define CLK_ACLK_AHB2APB_PERIC2P … #define CLK_ACLK_AHB2APB_PERIC1P … #define CLK_ACLK_AHB2APB_PERIC0P … #define CLK_ACLK_PERICNP_66 … #define CLK_PCLK_SCI … #define CLK_PCLK_GPIO_FINGER … #define CLK_PCLK_GPIO_ESE … #define CLK_PCLK_PWM … #define CLK_PCLK_SPDIF … #define CLK_PCLK_PCM1 … #define CLK_PCLK_I2S1 … #define CLK_PCLK_ADCIF … #define CLK_PCLK_GPIO_TOUCH … #define CLK_PCLK_GPIO_NFC … #define CLK_PCLK_GPIO_PERIC … #define CLK_PCLK_PMU_PERIC … #define CLK_PCLK_SYSREG_PERIC … #define CLK_SCLK_IOCLK_SPI4 … #define CLK_SCLK_IOCLK_SPI3 … #define CLK_SCLK_SCI … #define CLK_SCLK_SC_IN … #define CLK_SCLK_PWM … #define CLK_SCLK_IOCLK_SPI2 … #define CLK_SCLK_IOCLK_SPI1 … #define CLK_SCLK_IOCLK_SPI0 … #define CLK_SCLK_IOCLK_I2S1_BCLK … #define CLK_SCLK_SPDIF … #define CLK_SCLK_PCM1 … #define CLK_SCLK_I2S1 … #define CLK_DIV_SCLK_SCI … #define CLK_DIV_SCLK_SC_IN … /* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF … #define CLK_PCLK_TMU1_APBIF … #define CLK_PCLK_TMU0_APBIF … #define CLK_PCLK_PMU_PERIS … #define CLK_PCLK_SYSREG_PERIS … #define CLK_PCLK_CMU_TOP_APBIF … #define CLK_PCLK_WDT_APOLLO … #define CLK_PCLK_WDT_ATLAS … #define CLK_PCLK_MCT … #define CLK_PCLK_HDMI_CEC … #define CLK_ACLK_AHB2APB_PERIS1P … #define CLK_ACLK_AHB2APB_PERIS0P … #define CLK_ACLK_PERISNP_66 … #define CLK_PCLK_TZPC12 … #define CLK_PCLK_TZPC11 … #define CLK_PCLK_TZPC10 … #define CLK_PCLK_TZPC9 … #define CLK_PCLK_TZPC8 … #define CLK_PCLK_TZPC7 … #define CLK_PCLK_TZPC6 … #define CLK_PCLK_TZPC5 … #define CLK_PCLK_TZPC4 … #define CLK_PCLK_TZPC3 … #define CLK_PCLK_TZPC2 … #define CLK_PCLK_TZPC1 … #define CLK_PCLK_TZPC0 … #define CLK_PCLK_SECKEY_APBIF … #define CLK_PCLK_CHIPID_APBIF … #define CLK_PCLK_TOPRTC … #define CLK_PCLK_CUSTOM_EFUSE_APBIF … #define CLK_PCLK_ANTIRBK_CNT_APBIF … #define CLK_PCLK_OTP_CON_APBIF … #define CLK_SCLK_ASV_TB … #define CLK_SCLK_TMU1 … #define CLK_SCLK_TMU0 … #define CLK_SCLK_SECKEY … #define CLK_SCLK_CHIPID … #define CLK_SCLK_TOPRTC … #define CLK_SCLK_CUSTOM_EFUSE … #define CLK_SCLK_ANTIRBK_CNT … #define CLK_SCLK_OTP_CON … /* CMU_FSYS */ #define CLK_MOUT_ACLK_FSYS_200_USER … #define CLK_MOUT_SCLK_MMC2_USER … #define CLK_MOUT_SCLK_MMC1_USER … #define CLK_MOUT_SCLK_MMC0_USER … #define CLK_MOUT_SCLK_UFS_MPHY_USER … #define CLK_MOUT_SCLK_PCIE_100_USER … #define CLK_MOUT_SCLK_UFSUNIPRO_USER … #define CLK_MOUT_SCLK_USBHOST30_USER … #define CLK_MOUT_SCLK_USBDRD30_USER … #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER … #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER … #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER … #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER … #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER … #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER … #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER … #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER … #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER … #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER … #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER … #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER … #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER … #define CLK_MOUT_SCLK_MPHY … #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY … #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY … #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY … #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY … #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY … #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY … #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY … #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY … #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY … #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY … #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY … #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY … #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY … #define CLK_ACLK_PCIE … #define CLK_ACLK_PDMA1 … #define CLK_ACLK_TSI … #define CLK_ACLK_MMC2 … #define CLK_ACLK_MMC1 … #define CLK_ACLK_MMC0 … #define CLK_ACLK_UFS … #define CLK_ACLK_USBHOST20 … #define CLK_ACLK_USBHOST30 … #define CLK_ACLK_USBDRD30 … #define CLK_ACLK_PDMA0 … #define CLK_SCLK_MMC2 … #define CLK_SCLK_MMC1 … #define CLK_SCLK_MMC0 … #define CLK_PDMA1 … #define CLK_PDMA0 … #define CLK_ACLK_XIU_FSYSPX … #define CLK_ACLK_AHB_USBLINKH1 … #define CLK_ACLK_SMMU_PDMA1 … #define CLK_ACLK_BTS_PCIE … #define CLK_ACLK_AXIUS_PDMA1 … #define CLK_ACLK_SMMU_PDMA0 … #define CLK_ACLK_BTS_UFS … #define CLK_ACLK_BTS_USBHOST30 … #define CLK_ACLK_BTS_USBDRD30 … #define CLK_ACLK_AXIUS_PDMA0 … #define CLK_ACLK_AXIUS_USBHS … #define CLK_ACLK_AXIUS_FSYSSX … #define CLK_ACLK_AHB2APB_FSYSP … #define CLK_ACLK_AHB2AXI_USBHS … #define CLK_ACLK_AHB_USBLINKH0 … #define CLK_ACLK_AHB_USBHS … #define CLK_ACLK_AHB_FSYSH … #define CLK_ACLK_XIU_FSYSX … #define CLK_ACLK_XIU_FSYSSX … #define CLK_ACLK_FSYSNP_200 … #define CLK_ACLK_FSYSND_200 … #define CLK_PCLK_PCIE_CTRL … #define CLK_PCLK_SMMU_PDMA1 … #define CLK_PCLK_PCIE_PHY … #define CLK_PCLK_BTS_PCIE … #define CLK_PCLK_SMMU_PDMA0 … #define CLK_PCLK_BTS_UFS … #define CLK_PCLK_BTS_USBHOST30 … #define CLK_PCLK_BTS_USBDRD30 … #define CLK_PCLK_GPIO_FSYS … #define CLK_PCLK_PMU_FSYS … #define CLK_PCLK_SYSREG_FSYS … #define CLK_SCLK_PCIE_100 … #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK … #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK … #define CLK_PHYCLK_UFS_RX1_SYMBOL … #define CLK_PHYCLK_UFS_RX0_SYMBOL … #define CLK_PHYCLK_UFS_TX1_SYMBOL … #define CLK_PHYCLK_UFS_TX0_SYMBOL … #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 … #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI … #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK … #define CLK_PHYCLK_USBHOST20_PHY_FREECLK … #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK … #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK … #define CLK_SCLK_MPHY … #define CLK_SCLK_UFSUNIPRO … #define CLK_SCLK_USBHOST30 … #define CLK_SCLK_USBDRD30 … #define CLK_PCIE … /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER … #define CLK_MUX_ACLK_G2D_400_USER … #define CLK_DIV_PCLK_G2D … #define CLK_ACLK_SMMU_MDMA1 … #define CLK_ACLK_BTS_MDMA1 … #define CLK_ACLK_BTS_G2D … #define CLK_ACLK_ALB_G2D … #define CLK_ACLK_AXIUS_G2DX … #define CLK_ACLK_ASYNCAXI_SYSX … #define CLK_ACLK_AHB2APB_G2D1P … #define CLK_ACLK_AHB2APB_G2D0P … #define CLK_ACLK_XIU_G2DX … #define CLK_ACLK_G2DNP_133 … #define CLK_ACLK_G2DND_400 … #define CLK_ACLK_MDMA1 … #define CLK_ACLK_G2D … #define CLK_ACLK_SMMU_G2D … #define CLK_PCLK_SMMU_MDMA1 … #define CLK_PCLK_BTS_MDMA1 … #define CLK_PCLK_BTS_G2D … #define CLK_PCLK_ALB_G2D … #define CLK_PCLK_ASYNCAXI_SYSX … #define CLK_PCLK_PMU_G2D … #define CLK_PCLK_SYSREG_G2D … #define CLK_PCLK_G2D … #define CLK_PCLK_SMMU_G2D … /* CMU_DISP */ #define CLK_FOUT_DISP_PLL … #define CLK_MOUT_DISP_PLL … #define CLK_MOUT_SCLK_DSIM1_USER … #define CLK_MOUT_SCLK_DSIM0_USER … #define CLK_MOUT_SCLK_DSD_USER … #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER … #define CLK_MOUT_SCLK_DECON_VCLK_USER … #define CLK_MOUT_SCLK_DECON_ECLK_USER … #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER … #define CLK_MOUT_ACLK_DISP_333_USER … #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER … #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER … #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER … #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER … #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER … #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER … #define CLK_MOUT_SCLK_DSIM0 … #define CLK_MOUT_SCLK_DECON_TV_ECLK … #define CLK_MOUT_SCLK_DECON_VCLK … #define CLK_MOUT_SCLK_DECON_ECLK … #define CLK_MOUT_SCLK_DSIM1_B_DISP … #define CLK_MOUT_SCLK_DSIM1_A_DISP … #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP … #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP … #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP … #define CLK_DIV_SCLK_DSIM1_DISP … #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP … #define CLK_DIV_SCLK_DSIM0_DISP … #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP … #define CLK_DIV_SCLK_DECON_VCLK_DISP … #define CLK_DIV_SCLK_DECON_ECLK_DISP … #define CLK_DIV_PCLK_DISP … #define CLK_ACLK_DECON_TV … #define CLK_ACLK_DECON … #define CLK_ACLK_SMMU_TV1X … #define CLK_ACLK_SMMU_TV0X … #define CLK_ACLK_SMMU_DECON1X … #define CLK_ACLK_SMMU_DECON0X … #define CLK_ACLK_BTS_DECON_TV_M3 … #define CLK_ACLK_BTS_DECON_TV_M2 … #define CLK_ACLK_BTS_DECON_TV_M1 … #define CLK_ACLK_BTS_DECON_TV_M0 … #define CLK_ACLK_BTS_DECON_NM4 … #define CLK_ACLK_BTS_DECON_NM3 … #define CLK_ACLK_BTS_DECON_NM2 … #define CLK_ACLK_BTS_DECON_NM1 … #define CLK_ACLK_BTS_DECON_NM0 … #define CLK_ACLK_AHB2APB_DISPSFR2P … #define CLK_ACLK_AHB2APB_DISPSFR1P … #define CLK_ACLK_AHB2APB_DISPSFR0P … #define CLK_ACLK_AHB_DISPH … #define CLK_ACLK_XIU_TV1X … #define CLK_ACLK_XIU_TV0X … #define CLK_ACLK_XIU_DECON1X … #define CLK_ACLK_XIU_DECON0X … #define CLK_ACLK_XIU_DISP1X … #define CLK_ACLK_XIU_DISPNP_100 … #define CLK_ACLK_DISP1ND_333 … #define CLK_ACLK_DISP0ND_333 … #define CLK_PCLK_SMMU_TV1X … #define CLK_PCLK_SMMU_TV0X … #define CLK_PCLK_SMMU_DECON1X … #define CLK_PCLK_SMMU_DECON0X … #define CLK_PCLK_BTS_DECON_TV_M3 … #define CLK_PCLK_BTS_DECON_TV_M2 … #define CLK_PCLK_BTS_DECON_TV_M1 … #define CLK_PCLK_BTS_DECON_TV_M0 … #define CLK_PCLK_BTS_DECONM4 … #define CLK_PCLK_BTS_DECONM3 … #define CLK_PCLK_BTS_DECONM2 … #define CLK_PCLK_BTS_DECONM1 … #define CLK_PCLK_BTS_DECONM0 … #define CLK_PCLK_MIC1 … #define CLK_PCLK_PMU_DISP … #define CLK_PCLK_SYSREG_DISP … #define CLK_PCLK_HDMIPHY … #define CLK_PCLK_HDMI … #define CLK_PCLK_MIC0 … #define CLK_PCLK_DSIM1 … #define CLK_PCLK_DSIM0 … #define CLK_PCLK_DECON_TV … #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 … #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 … #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 … #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 … #define CLK_SCLK_DSIM1 … #define CLK_SCLK_DECON_TV_VCLK … #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 … #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 … #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO … #define CLK_PHYCLK_HDMI_PIXEL … #define CLK_SCLK_RGB_VCLK_TO_SMIES … #define CLK_SCLK_FREQ_DET_DISP_PLL … #define CLK_SCLK_RGB_VCLK_TO_DSIM0 … #define CLK_SCLK_RGB_VCLK_TO_MIC0 … #define CLK_SCLK_DSD … #define CLK_SCLK_HDMI_SPDIF … #define CLK_SCLK_DSIM0 … #define CLK_SCLK_DECON_TV_ECLK … #define CLK_SCLK_DECON_VCLK … #define CLK_SCLK_DECON_ECLK … #define CLK_SCLK_RGB_VCLK … #define CLK_SCLK_RGB_TV_VCLK … #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY … #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY … #define CLK_PCLK_DECON … #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY … #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY … /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER … #define CLK_MOUT_SCLK_AUD_PCM … #define CLK_MOUT_SCLK_AUD_I2S … #define CLK_DIV_ATCLK_AUD … #define CLK_DIV_PCLK_DBG_AUD … #define CLK_DIV_ACLK_AUD … #define CLK_DIV_AUD_CA5 … #define CLK_DIV_SCLK_AUD_SLIMBUS … #define CLK_DIV_SCLK_AUD_UART … #define CLK_DIV_SCLK_AUD_PCM … #define CLK_DIV_SCLK_AUD_I2S … #define CLK_ACLK_INTR_CTRL … #define CLK_ACLK_AXIDS2_LPASSP … #define CLK_ACLK_AXIDS1_LPASSP … #define CLK_ACLK_AXI2APB1_LPASSP … #define CLK_ACLK_AXI2APH_LPASSP … #define CLK_ACLK_SMMU_LPASSX … #define CLK_ACLK_AXIDS0_LPASSP … #define CLK_ACLK_AXI2APB0_LPASSP … #define CLK_ACLK_XIU_LPASSX … #define CLK_ACLK_AUDNP_133 … #define CLK_ACLK_AUDND_133 … #define CLK_ACLK_SRAMC … #define CLK_ACLK_DMAC … #define CLK_PCLK_WDT1 … #define CLK_PCLK_WDT0 … #define CLK_PCLK_SFR1 … #define CLK_PCLK_SMMU_LPASSX … #define CLK_PCLK_GPIO_AUD … #define CLK_PCLK_PMU_AUD … #define CLK_PCLK_SYSREG_AUD … #define CLK_PCLK_AUD_SLIMBUS … #define CLK_PCLK_AUD_UART … #define CLK_PCLK_AUD_PCM … #define CLK_PCLK_AUD_I2S … #define CLK_PCLK_TIMER … #define CLK_PCLK_SFR0_CTRL … #define CLK_ATCLK_AUD … #define CLK_PCLK_DBG_AUD … #define CLK_SCLK_AUD_CA5 … #define CLK_SCLK_JTAG_TCK … #define CLK_SCLK_SLIMBUS_CLKIN … #define CLK_SCLK_AUD_SLIMBUS … #define CLK_SCLK_AUD_UART … #define CLK_SCLK_AUD_PCM … #define CLK_SCLK_I2S_BCLK … #define CLK_SCLK_AUD_I2S … /* CMU_BUS{0|1|2} */ #define CLK_DIV_PCLK_BUS_133 … #define CLK_ACLK_AHB2APB_BUSP … #define CLK_ACLK_BUSNP_133 … #define CLK_ACLK_BUSND_400 … #define CLK_PCLK_BUSSRVND_133 … #define CLK_PCLK_PMU_BUS … #define CLK_PCLK_SYSREG_BUS … #define CLK_MOUT_ACLK_BUS2_400_USER … #define CLK_ACLK_BUS2BEND_400 … #define CLK_ACLK_BUS2RTND_400 … /* CMU_G3D */ #define CLK_FOUT_G3D_PLL … #define CLK_MOUT_ACLK_G3D_400 … #define CLK_MOUT_G3D_PLL … #define CLK_DIV_SCLK_HPM_G3D … #define CLK_DIV_PCLK_G3D … #define CLK_DIV_ACLK_G3D … #define CLK_ACLK_BTS_G3D1 … #define CLK_ACLK_BTS_G3D0 … #define CLK_ACLK_ASYNCAPBS_G3D … #define CLK_ACLK_ASYNCAPBM_G3D … #define CLK_ACLK_AHB2APB_G3DP … #define CLK_ACLK_G3DNP_150 … #define CLK_ACLK_G3DND_600 … #define CLK_ACLK_G3D … #define CLK_PCLK_BTS_G3D1 … #define CLK_PCLK_BTS_G3D0 … #define CLK_PCLK_PMU_G3D … #define CLK_PCLK_SYSREG_G3D … #define CLK_SCLK_HPM_G3D … /* CMU_GSCL */ #define CLK_MOUT_ACLK_GSCL_111_USER … #define CLK_MOUT_ACLK_GSCL_333_USER … #define CLK_ACLK_BTS_GSCL2 … #define CLK_ACLK_BTS_GSCL1 … #define CLK_ACLK_BTS_GSCL0 … #define CLK_ACLK_AHB2APB_GSCLP … #define CLK_ACLK_XIU_GSCLX … #define CLK_ACLK_GSCLNP_111 … #define CLK_ACLK_GSCLRTND_333 … #define CLK_ACLK_GSCLBEND_333 … #define CLK_ACLK_GSD … #define CLK_ACLK_GSCL2 … #define CLK_ACLK_GSCL1 … #define CLK_ACLK_GSCL0 … #define CLK_ACLK_SMMU_GSCL0 … #define CLK_ACLK_SMMU_GSCL1 … #define CLK_ACLK_SMMU_GSCL2 … #define CLK_PCLK_BTS_GSCL2 … #define CLK_PCLK_BTS_GSCL1 … #define CLK_PCLK_BTS_GSCL0 … #define CLK_PCLK_PMU_GSCL … #define CLK_PCLK_SYSREG_GSCL … #define CLK_PCLK_GSCL2 … #define CLK_PCLK_GSCL1 … #define CLK_PCLK_GSCL0 … #define CLK_PCLK_SMMU_GSCL0 … #define CLK_PCLK_SMMU_GSCL1 … #define CLK_PCLK_SMMU_GSCL2 … /* CMU_APOLLO */ #define CLK_FOUT_APOLLO_PLL … #define CLK_MOUT_APOLLO_PLL … #define CLK_MOUT_BUS_PLL_APOLLO_USER … #define CLK_MOUT_APOLLO … #define CLK_DIV_CNTCLK_APOLLO … #define CLK_DIV_PCLK_DBG_APOLLO … #define CLK_DIV_ATCLK_APOLLO … #define CLK_DIV_PCLK_APOLLO … #define CLK_DIV_ACLK_APOLLO … #define CLK_DIV_APOLLO2 … #define CLK_DIV_APOLLO1 … #define CLK_DIV_SCLK_HPM_APOLLO … #define CLK_DIV_APOLLO_PLL … #define CLK_ACLK_ATBDS_APOLLO_3 … #define CLK_ACLK_ATBDS_APOLLO_2 … #define CLK_ACLK_ATBDS_APOLLO_1 … #define CLK_ACLK_ATBDS_APOLLO_0 … #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS … #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS … #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS … #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS … #define CLK_ACLK_ASYNCACES_APOLLO_CCI … #define CLK_ACLK_AHB2APB_APOLLOP … #define CLK_ACLK_APOLLONP_200 … #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO … #define CLK_PCLK_PMU_APOLLO … #define CLK_PCLK_SYSREG_APOLLO … #define CLK_CNTCLK_APOLLO … #define CLK_SCLK_HPM_APOLLO … #define CLK_SCLK_APOLLO … /* CMU_ATLAS */ #define CLK_FOUT_ATLAS_PLL … #define CLK_MOUT_ATLAS_PLL … #define CLK_MOUT_BUS_PLL_ATLAS_USER … #define CLK_MOUT_ATLAS … #define CLK_DIV_CNTCLK_ATLAS … #define CLK_DIV_PCLK_DBG_ATLAS … #define CLK_DIV_ATCLK_ATLASO … #define CLK_DIV_PCLK_ATLAS … #define CLK_DIV_ACLK_ATLAS … #define CLK_DIV_ATLAS2 … #define CLK_DIV_ATLAS1 … #define CLK_DIV_SCLK_HPM_ATLAS … #define CLK_DIV_ATLAS_PLL … #define CLK_ACLK_ATB_AUD_CSSYS … #define CLK_ACLK_ATB_APOLLO3_CSSYS … #define CLK_ACLK_ATB_APOLLO2_CSSYS … #define CLK_ACLK_ATB_APOLLO1_CSSYS … #define CLK_ACLK_ATB_APOLLO0_CSSYS … #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS … #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX … #define CLK_ACLK_ASYNCACES_ATLAS_CCI … #define CLK_ACLK_AHB2APB_ATLASP … #define CLK_ACLK_ATLASNP_200 … #define CLK_PCLK_ASYNCAPB_AUD_CSSYS … #define CLK_PCLK_ASYNCAPB_ISP_CSSYS … #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS … #define CLK_PCLK_PMU_ATLAS … #define CLK_PCLK_SYSREG_ATLAS … #define CLK_PCLK_SECJTAG … #define CLK_CNTCLK_ATLAS … #define CLK_SCLK_FREQ_DET_ATLAS_PLL … #define CLK_SCLK_HPM_ATLAS … #define CLK_TRACECLK … #define CLK_CTMCLK … #define CLK_HCLK_CSSYS … #define CLK_PCLK_DBG_CSSYS … #define CLK_PCLK_DBG … #define CLK_ATCLK … #define CLK_SCLK_ATLAS … /* CMU_MSCL */ #define CLK_MOUT_SCLK_JPEG_USER … #define CLK_MOUT_ACLK_MSCL_400_USER … #define CLK_MOUT_SCLK_JPEG … #define CLK_DIV_PCLK_MSCL … #define CLK_ACLK_BTS_JPEG … #define CLK_ACLK_BTS_M2MSCALER1 … #define CLK_ACLK_BTS_M2MSCALER0 … #define CLK_ACLK_AHB2APB_MSCL0P … #define CLK_ACLK_XIU_MSCLX … #define CLK_ACLK_MSCLNP_100 … #define CLK_ACLK_MSCLND_400 … #define CLK_ACLK_JPEG … #define CLK_ACLK_M2MSCALER1 … #define CLK_ACLK_M2MSCALER0 … #define CLK_ACLK_SMMU_M2MSCALER0 … #define CLK_ACLK_SMMU_M2MSCALER1 … #define CLK_ACLK_SMMU_JPEG … #define CLK_PCLK_BTS_JPEG … #define CLK_PCLK_BTS_M2MSCALER1 … #define CLK_PCLK_BTS_M2MSCALER0 … #define CLK_PCLK_PMU_MSCL … #define CLK_PCLK_SYSREG_MSCL … #define CLK_PCLK_JPEG … #define CLK_PCLK_M2MSCALER1 … #define CLK_PCLK_M2MSCALER0 … #define CLK_PCLK_SMMU_M2MSCALER0 … #define CLK_PCLK_SMMU_M2MSCALER1 … #define CLK_PCLK_SMMU_JPEG … #define CLK_SCLK_JPEG … /* CMU_MFC */ #define CLK_MOUT_ACLK_MFC_400_USER … #define CLK_DIV_PCLK_MFC … #define CLK_ACLK_BTS_MFC_1 … #define CLK_ACLK_BTS_MFC_0 … #define CLK_ACLK_AHB2APB_MFCP … #define CLK_ACLK_XIU_MFCX … #define CLK_ACLK_MFCNP_100 … #define CLK_ACLK_MFCND_400 … #define CLK_ACLK_MFC … #define CLK_ACLK_SMMU_MFC_1 … #define CLK_ACLK_SMMU_MFC_0 … #define CLK_PCLK_BTS_MFC_1 … #define CLK_PCLK_BTS_MFC_0 … #define CLK_PCLK_PMU_MFC … #define CLK_PCLK_SYSREG_MFC … #define CLK_PCLK_MFC … #define CLK_PCLK_SMMU_MFC_1 … #define CLK_PCLK_SMMU_MFC_0 … /* CMU_HEVC */ #define CLK_MOUT_ACLK_HEVC_400_USER … #define CLK_DIV_PCLK_HEVC … #define CLK_ACLK_BTS_HEVC_1 … #define CLK_ACLK_BTS_HEVC_0 … #define CLK_ACLK_AHB2APB_HEVCP … #define CLK_ACLK_XIU_HEVCX … #define CLK_ACLK_HEVCNP_100 … #define CLK_ACLK_HEVCND_400 … #define CLK_ACLK_HEVC … #define CLK_ACLK_SMMU_HEVC_1 … #define CLK_ACLK_SMMU_HEVC_0 … #define CLK_PCLK_BTS_HEVC_1 … #define CLK_PCLK_BTS_HEVC_0 … #define CLK_PCLK_PMU_HEVC … #define CLK_PCLK_SYSREG_HEVC … #define CLK_PCLK_HEVC … #define CLK_PCLK_SMMU_HEVC_1 … #define CLK_PCLK_SMMU_HEVC_0 … /* CMU_ISP */ #define CLK_MOUT_ACLK_ISP_DIS_400_USER … #define CLK_MOUT_ACLK_ISP_400_USER … #define CLK_DIV_PCLK_ISP_DIS … #define CLK_DIV_PCLK_ISP … #define CLK_DIV_ACLK_ISP_D_200 … #define CLK_DIV_ACLK_ISP_C_200 … #define CLK_ACLK_ISP_D_GLUE … #define CLK_ACLK_SCALERP … #define CLK_ACLK_3DNR … #define CLK_ACLK_DIS … #define CLK_ACLK_SCALERC … #define CLK_ACLK_DRC … #define CLK_ACLK_ISP … #define CLK_ACLK_AXIUS_SCALERP … #define CLK_ACLK_AXIUS_SCALERC … #define CLK_ACLK_AXIUS_DRC … #define CLK_ACLK_ASYNCAHBM_ISP2P … #define CLK_ACLK_ASYNCAHBM_ISP1P … #define CLK_ACLK_ASYNCAXIS_DIS1 … #define CLK_ACLK_ASYNCAXIS_DIS0 … #define CLK_ACLK_ASYNCAXIM_DIS1 … #define CLK_ACLK_ASYNCAXIM_DIS0 … #define CLK_ACLK_ASYNCAXIM_ISP2P … #define CLK_ACLK_ASYNCAXIM_ISP1P … #define CLK_ACLK_AHB2APB_ISP2P … #define CLK_ACLK_AHB2APB_ISP1P … #define CLK_ACLK_AXI2APB_ISP2P … #define CLK_ACLK_AXI2APB_ISP1P … #define CLK_ACLK_XIU_ISPEX1 … #define CLK_ACLK_XIU_ISPEX0 … #define CLK_ACLK_ISPND_400 … #define CLK_ACLK_SMMU_SCALERP … #define CLK_ACLK_SMMU_3DNR … #define CLK_ACLK_SMMU_DIS1 … #define CLK_ACLK_SMMU_DIS0 … #define CLK_ACLK_SMMU_SCALERC … #define CLK_ACLK_SMMU_DRC … #define CLK_ACLK_SMMU_ISP … #define CLK_ACLK_BTS_SCALERP … #define CLK_ACLK_BTS_3DR … #define CLK_ACLK_BTS_DIS1 … #define CLK_ACLK_BTS_DIS0 … #define CLK_ACLK_BTS_SCALERC … #define CLK_ACLK_BTS_DRC … #define CLK_ACLK_BTS_ISP … #define CLK_PCLK_SMMU_SCALERP … #define CLK_PCLK_SMMU_3DNR … #define CLK_PCLK_SMMU_DIS1 … #define CLK_PCLK_SMMU_DIS0 … #define CLK_PCLK_SMMU_SCALERC … #define CLK_PCLK_SMMU_DRC … #define CLK_PCLK_SMMU_ISP … #define CLK_PCLK_BTS_SCALERP … #define CLK_PCLK_BTS_3DNR … #define CLK_PCLK_BTS_DIS1 … #define CLK_PCLK_BTS_DIS0 … #define CLK_PCLK_BTS_SCALERC … #define CLK_PCLK_BTS_DRC … #define CLK_PCLK_BTS_ISP … #define CLK_PCLK_ASYNCAXI_DIS1 … #define CLK_PCLK_ASYNCAXI_DIS0 … #define CLK_PCLK_PMU_ISP … #define CLK_PCLK_SYSREG_ISP … #define CLK_PCLK_CMU_ISP_LOCAL … #define CLK_PCLK_SCALERP … #define CLK_PCLK_3DNR … #define CLK_PCLK_DIS_CORE … #define CLK_PCLK_DIS … #define CLK_PCLK_SCALERC … #define CLK_PCLK_DRC … #define CLK_PCLK_ISP … #define CLK_SCLK_PIXELASYNCS_DIS … #define CLK_SCLK_PIXELASYNCM_DIS … #define CLK_SCLK_PIXELASYNCS_SCALERP … #define CLK_SCLK_PIXELASYNCM_ISPD … #define CLK_SCLK_PIXELASYNCS_ISPC … #define CLK_SCLK_PIXELASYNCM_ISPC … /* CMU_CAM0 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY … #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY … #define CLK_MOUT_ACLK_CAM0_333_USER … #define CLK_MOUT_ACLK_CAM0_400_USER … #define CLK_MOUT_ACLK_CAM0_552_USER … #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER … #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER … #define CLK_MOUT_ACLK_LITE_D_B … #define CLK_MOUT_ACLK_LITE_D_A … #define CLK_MOUT_ACLK_LITE_B_B … #define CLK_MOUT_ACLK_LITE_B_A … #define CLK_MOUT_ACLK_LITE_A_B … #define CLK_MOUT_ACLK_LITE_A_A … #define CLK_MOUT_ACLK_CAM0_400 … #define CLK_MOUT_ACLK_CSIS1_B … #define CLK_MOUT_ACLK_CSIS1_A … #define CLK_MOUT_ACLK_CSIS0_B … #define CLK_MOUT_ACLK_CSIS0_A … #define CLK_MOUT_ACLK_3AA1_B … #define CLK_MOUT_ACLK_3AA1_A … #define CLK_MOUT_ACLK_3AA0_B … #define CLK_MOUT_ACLK_3AA0_A … #define CLK_MOUT_SCLK_LITE_FREECNT_C … #define CLK_MOUT_SCLK_LITE_FREECNT_B … #define CLK_MOUT_SCLK_LITE_FREECNT_A … #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B … #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A … #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B … #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A … #define CLK_DIV_PCLK_CAM0_50 … #define CLK_DIV_ACLK_CAM0_200 … #define CLK_DIV_ACLK_CAM0_BUS_400 … #define CLK_DIV_PCLK_LITE_D … #define CLK_DIV_ACLK_LITE_D … #define CLK_DIV_PCLK_LITE_B … #define CLK_DIV_ACLK_LITE_B … #define CLK_DIV_PCLK_LITE_A … #define CLK_DIV_ACLK_LITE_A … #define CLK_DIV_ACLK_CSIS1 … #define CLK_DIV_ACLK_CSIS0 … #define CLK_DIV_PCLK_3AA1 … #define CLK_DIV_ACLK_3AA1 … #define CLK_DIV_PCLK_3AA0 … #define CLK_DIV_ACLK_3AA0 … #define CLK_DIV_SCLK_PIXELASYNC_LITE_C … #define CLK_DIV_PCLK_PIXELASYNC_LITE_C … #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT … #define CLK_ACLK_CSIS1 … #define CLK_ACLK_CSIS0 … #define CLK_ACLK_3AA1 … #define CLK_ACLK_3AA0 … #define CLK_ACLK_LITE_D … #define CLK_ACLK_LITE_B … #define CLK_ACLK_LITE_A … #define CLK_ACLK_AHBSYNCDN … #define CLK_ACLK_AXIUS_LITE_D … #define CLK_ACLK_AXIUS_LITE_B … #define CLK_ACLK_AXIUS_LITE_A … #define CLK_ACLK_ASYNCAPBM_3AA1 … #define CLK_ACLK_ASYNCAPBS_3AA1 … #define CLK_ACLK_ASYNCAPBM_3AA0 … #define CLK_ACLK_ASYNCAPBS_3AA0 … #define CLK_ACLK_ASYNCAPBM_LITE_D … #define CLK_ACLK_ASYNCAPBS_LITE_D … #define CLK_ACLK_ASYNCAPBM_LITE_B … #define CLK_ACLK_ASYNCAPBS_LITE_B … #define CLK_ACLK_ASYNCAPBM_LITE_A … #define CLK_ACLK_ASYNCAPBS_LITE_A … #define CLK_ACLK_ASYNCAXIM_ISP0P … #define CLK_ACLK_ASYNCAXIM_3AA1 … #define CLK_ACLK_ASYNCAXIS_3AA1 … #define CLK_ACLK_ASYNCAXIM_3AA0 … #define CLK_ACLK_ASYNCAXIS_3AA0 … #define CLK_ACLK_ASYNCAXIM_LITE_D … #define CLK_ACLK_ASYNCAXIS_LITE_D … #define CLK_ACLK_ASYNCAXIM_LITE_B … #define CLK_ACLK_ASYNCAXIS_LITE_B … #define CLK_ACLK_ASYNCAXIM_LITE_A … #define CLK_ACLK_ASYNCAXIS_LITE_A … #define CLK_ACLK_AHB2APB_ISPSFRP … #define CLK_ACLK_AXI2APB_ISP0P … #define CLK_ACLK_AXI2AHB_ISP0P … #define CLK_ACLK_XIU_IS0X … #define CLK_ACLK_XIU_ISP0EX … #define CLK_ACLK_CAM0NP_276 … #define CLK_ACLK_CAM0ND_400 … #define CLK_ACLK_SMMU_3AA1 … #define CLK_ACLK_SMMU_3AA0 … #define CLK_ACLK_SMMU_LITE_D … #define CLK_ACLK_SMMU_LITE_B … #define CLK_ACLK_SMMU_LITE_A … #define CLK_ACLK_BTS_3AA1 … #define CLK_ACLK_BTS_3AA0 … #define CLK_ACLK_BTS_LITE_D … #define CLK_ACLK_BTS_LITE_B … #define CLK_ACLK_BTS_LITE_A … #define CLK_PCLK_SMMU_3AA1 … #define CLK_PCLK_SMMU_3AA0 … #define CLK_PCLK_SMMU_LITE_D … #define CLK_PCLK_SMMU_LITE_B … #define CLK_PCLK_SMMU_LITE_A … #define CLK_PCLK_BTS_3AA1 … #define CLK_PCLK_BTS_3AA0 … #define CLK_PCLK_BTS_LITE_D … #define CLK_PCLK_BTS_LITE_B … #define CLK_PCLK_BTS_LITE_A … #define CLK_PCLK_ASYNCAXI_CAM1 … #define CLK_PCLK_ASYNCAXI_3AA1 … #define CLK_PCLK_ASYNCAXI_3AA0 … #define CLK_PCLK_ASYNCAXI_LITE_D … #define CLK_PCLK_ASYNCAXI_LITE_B … #define CLK_PCLK_ASYNCAXI_LITE_A … #define CLK_PCLK_PMU_CAM0 … #define CLK_PCLK_SYSREG_CAM0 … #define CLK_PCLK_CMU_CAM0_LOCAL … #define CLK_PCLK_CSIS1 … #define CLK_PCLK_CSIS0 … #define CLK_PCLK_3AA1 … #define CLK_PCLK_3AA0 … #define CLK_PCLK_LITE_D … #define CLK_PCLK_LITE_B … #define CLK_PCLK_LITE_A … #define CLK_PHYCLK_RXBYTECLKHS0_S4 … #define CLK_PHYCLK_RXBYTECLKHS0_S2A … #define CLK_SCLK_LITE_FREECNT … #define CLK_SCLK_PIXELASYNCM_3AA1 … #define CLK_SCLK_PIXELASYNCM_3AA0 … #define CLK_SCLK_PIXELASYNCS_3AA0 … #define CLK_SCLK_PIXELASYNCM_LITE_C … #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT … #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT … /* CMU_CAM1 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S2B … #define CLK_MOUT_SCLK_ISP_UART_USER … #define CLK_MOUT_SCLK_ISP_SPI1_USER … #define CLK_MOUT_SCLK_ISP_SPI0_USER … #define CLK_MOUT_ACLK_CAM1_333_USER … #define CLK_MOUT_ACLK_CAM1_400_USER … #define CLK_MOUT_ACLK_CAM1_552_USER … #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER … #define CLK_MOUT_ACLK_CSIS2_B … #define CLK_MOUT_ACLK_CSIS2_A … #define CLK_MOUT_ACLK_FD_B … #define CLK_MOUT_ACLK_FD_A … #define CLK_MOUT_ACLK_LITE_C_B … #define CLK_MOUT_ACLK_LITE_C_A … #define CLK_DIV_SCLK_ISP_MPWM … #define CLK_DIV_PCLK_CAM1_83 … #define CLK_DIV_PCLK_CAM1_166 … #define CLK_DIV_PCLK_DBG_CAM1 … #define CLK_DIV_ATCLK_CAM1 … #define CLK_DIV_ACLK_CSIS2 … #define CLK_DIV_PCLK_FD … #define CLK_DIV_ACLK_FD … #define CLK_DIV_PCLK_LITE_C … #define CLK_DIV_ACLK_LITE_C … #define CLK_ACLK_ISP_GIC … #define CLK_ACLK_FD … #define CLK_ACLK_LITE_C … #define CLK_ACLK_CSIS2 … #define CLK_ACLK_ASYNCAPBM_FD … #define CLK_ACLK_ASYNCAPBS_FD … #define CLK_ACLK_ASYNCAPBM_LITE_C … #define CLK_ACLK_ASYNCAPBS_LITE_C … #define CLK_ACLK_ASYNCAHBS_SFRISP2H2 … #define CLK_ACLK_ASYNCAHBS_SFRISP2H1 … #define CLK_ACLK_ASYNCAXIM_CA5 … #define CLK_ACLK_ASYNCAXIS_CA5 … #define CLK_ACLK_ASYNCAXIS_ISPX2 … #define CLK_ACLK_ASYNCAXIS_ISPX1 … #define CLK_ACLK_ASYNCAXIS_ISPX0 … #define CLK_ACLK_ASYNCAXIM_ISPEX … #define CLK_ACLK_ASYNCAXIM_ISP3P … #define CLK_ACLK_ASYNCAXIS_ISP3P … #define CLK_ACLK_ASYNCAXIM_FD … #define CLK_ACLK_ASYNCAXIS_FD … #define CLK_ACLK_ASYNCAXIM_LITE_C … #define CLK_ACLK_ASYNCAXIS_LITE_C … #define CLK_ACLK_AHB2APB_ISP5P … #define CLK_ACLK_AHB2APB_ISP3P … #define CLK_ACLK_AXI2APB_ISP3P … #define CLK_ACLK_AHB_SFRISP2H … #define CLK_ACLK_AXI_ISP_HX_R … #define CLK_ACLK_AXI_ISP_CX_R … #define CLK_ACLK_AXI_ISP_HX … #define CLK_ACLK_AXI_ISP_CX … #define CLK_ACLK_XIU_ISPX … #define CLK_ACLK_XIU_ISPEX … #define CLK_ACLK_CAM1NP_333 … #define CLK_ACLK_CAM1ND_400 … #define CLK_ACLK_SMMU_ISPCPU … #define CLK_ACLK_SMMU_FD … #define CLK_ACLK_SMMU_LITE_C … #define CLK_ACLK_BTS_ISP3P … #define CLK_ACLK_BTS_FD … #define CLK_ACLK_BTS_LITE_C … #define CLK_ACLK_AHBDN_SFRISP2H … #define CLK_ACLK_AHBDN_ISP5P … #define CLK_ACLK_AXIUS_ISP3P … #define CLK_ACLK_AXIUS_FD … #define CLK_ACLK_AXIUS_LITE_C … #define CLK_PCLK_SMMU_ISPCPU … #define CLK_PCLK_SMMU_FD … #define CLK_PCLK_SMMU_LITE_C … #define CLK_PCLK_BTS_ISP3P … #define CLK_PCLK_BTS_FD … #define CLK_PCLK_BTS_LITE_C … #define CLK_PCLK_ASYNCAXIM_CA5 … #define CLK_PCLK_ASYNCAXIM_ISPEX … #define CLK_PCLK_ASYNCAXIM_ISP3P … #define CLK_PCLK_ASYNCAXIM_FD … #define CLK_PCLK_ASYNCAXIM_LITE_C … #define CLK_PCLK_PMU_CAM1 … #define CLK_PCLK_SYSREG_CAM1 … #define CLK_PCLK_CMU_CAM1_LOCAL … #define CLK_PCLK_ISP_MCTADC … #define CLK_PCLK_ISP_WDT … #define CLK_PCLK_ISP_PWM … #define CLK_PCLK_ISP_UART … #define CLK_PCLK_ISP_MCUCTL … #define CLK_PCLK_ISP_SPI1 … #define CLK_PCLK_ISP_SPI0 … #define CLK_PCLK_ISP_I2C2 … #define CLK_PCLK_ISP_I2C1 … #define CLK_PCLK_ISP_I2C0 … #define CLK_PCLK_ISP_MPWM … #define CLK_PCLK_FD … #define CLK_PCLK_LITE_C … #define CLK_PCLK_CSIS2 … #define CLK_SCLK_ISP_I2C2 … #define CLK_SCLK_ISP_I2C1 … #define CLK_SCLK_ISP_I2C0 … #define CLK_SCLK_ISP_PWM … #define CLK_PHYCLK_RXBYTECLKHS0_S2B … #define CLK_SCLK_LITE_C_FREECNT … #define CLK_SCLK_PIXELASYNCM_FD … #define CLK_SCLK_ISP_MCTADC … #define CLK_SCLK_ISP_UART … #define CLK_SCLK_ISP_SPI1 … #define CLK_SCLK_ISP_SPI0 … #define CLK_SCLK_ISP_MPWM … #define CLK_PCLK_DBG_ISP … #define CLK_ATCLK_ISP … #define CLK_SCLK_ISP_CA5 … /* CMU_IMEM */ #define CLK_ACLK_SLIMSSS … #define CLK_PCLK_SLIMSSS … #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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