// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * * This file contains the utility functions to register the pll clocks. */ #include <linux/errno.h> #include <linux/hrtimer.h> #include <linux/iopoll.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/timekeeping.h> #include <linux/clk-provider.h> #include <linux/io.h> #include "clk.h" #include "clk-pll.h" #define PLL_TIMEOUT_US … #define PLL_TIMEOUT_LOOPS … struct samsung_clk_pll { … }; #define to_clk_pll(_hw) … static const struct samsung_pll_rate_table *samsung_get_pll_settings( struct samsung_clk_pll *pll, unsigned long rate) { … } static long samsung_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { … } static bool pll_early_timeout = …; static int __init samsung_pll_disable_early_timeout(void) { … } arch_initcall(samsung_pll_disable_early_timeout); /* Wait until the PLL is locked */ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, unsigned int reg_mask) { … } static int samsung_pll3xxx_enable(struct clk_hw *hw) { … } static void samsung_pll3xxx_disable(struct clk_hw *hw) { … } /* * PLL2126 Clock Type */ #define PLL2126_MDIV_MASK … #define PLL2126_PDIV_MASK … #define PLL2126_SDIV_MASK … #define PLL2126_MDIV_SHIFT … #define PLL2126_PDIV_SHIFT … #define PLL2126_SDIV_SHIFT … static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll2126_clk_ops = …; /* * PLL3000 Clock Type */ #define PLL3000_MDIV_MASK … #define PLL3000_PDIV_MASK … #define PLL3000_SDIV_MASK … #define PLL3000_MDIV_SHIFT … #define PLL3000_PDIV_SHIFT … #define PLL3000_SDIV_SHIFT … static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll3000_clk_ops = …; /* * PLL35xx Clock Type */ /* Maximum lock time can be 270 * PDIV cycles */ #define PLL35XX_LOCK_FACTOR … #define PLL35XX_MDIV_MASK … #define PLL35XX_PDIV_MASK … #define PLL35XX_SDIV_MASK … #define PLL35XX_MDIV_SHIFT … #define PLL35XX_PDIV_SHIFT … #define PLL35XX_SDIV_SHIFT … #define PLL35XX_LOCK_STAT_SHIFT … #define PLL35XX_ENABLE_SHIFT … static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static inline bool samsung_pll35xx_mp_change( const struct samsung_pll_rate_table *rate, u32 pll_con) { … } static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll35xx_clk_ops = …; static const struct clk_ops samsung_pll35xx_clk_min_ops = …; /* * PLL36xx Clock Type */ /* Maximum lock time can be 3000 * PDIV cycles */ #define PLL36XX_LOCK_FACTOR … #define PLL36XX_KDIV_MASK … #define PLL36XX_MDIV_MASK … #define PLL36XX_PDIV_MASK … #define PLL36XX_SDIV_MASK … #define PLL36XX_MDIV_SHIFT … #define PLL36XX_PDIV_SHIFT … #define PLL36XX_SDIV_SHIFT … #define PLL36XX_KDIV_SHIFT … #define PLL36XX_LOCK_STAT_SHIFT … #define PLL36XX_ENABLE_SHIFT … static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static inline bool samsung_pll36xx_mpk_change( const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) { … } static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll36xx_clk_ops = …; static const struct clk_ops samsung_pll36xx_clk_min_ops = …; /* * PLL0822x Clock Type */ /* Maximum lock time can be 150 * PDIV cycles */ #define PLL0822X_LOCK_FACTOR … #define PLL0822X_MDIV_MASK … #define PLL0822X_PDIV_MASK … #define PLL0822X_SDIV_MASK … #define PLL0822X_MDIV_SHIFT … #define PLL0822X_PDIV_SHIFT … #define PLL0822X_SDIV_SHIFT … #define PLL0822X_LOCK_STAT_SHIFT … #define PLL0822X_ENABLE_SHIFT … static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll0822x_clk_ops = …; static const struct clk_ops samsung_pll0822x_clk_min_ops = …; /* * PLL0831x Clock Type */ /* Maximum lock time can be 500 * PDIV cycles */ #define PLL0831X_LOCK_FACTOR … #define PLL0831X_KDIV_MASK … #define PLL0831X_MDIV_MASK … #define PLL0831X_PDIV_MASK … #define PLL0831X_SDIV_MASK … #define PLL0831X_MDIV_SHIFT … #define PLL0831X_PDIV_SHIFT … #define PLL0831X_SDIV_SHIFT … #define PLL0831X_KDIV_SHIFT … #define PLL0831X_LOCK_STAT_SHIFT … #define PLL0831X_ENABLE_SHIFT … static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll0831x_clk_ops = …; static const struct clk_ops samsung_pll0831x_clk_min_ops = …; /* * PLL45xx Clock Type */ #define PLL4502_LOCK_FACTOR … #define PLL4508_LOCK_FACTOR … #define PLL45XX_MDIV_MASK … #define PLL45XX_PDIV_MASK … #define PLL45XX_SDIV_MASK … #define PLL45XX_AFC_MASK … #define PLL45XX_MDIV_SHIFT … #define PLL45XX_PDIV_SHIFT … #define PLL45XX_SDIV_SHIFT … #define PLL45XX_AFC_SHIFT … #define PLL45XX_ENABLE … #define PLL45XX_LOCKED … static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, const struct samsung_pll_rate_table *rate) { … } static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll45xx_clk_ops = …; static const struct clk_ops samsung_pll45xx_clk_min_ops = …; /* * PLL46xx Clock Type */ #define PLL46XX_LOCK_FACTOR … #define PLL46XX_VSEL_MASK … #define PLL46XX_MDIV_MASK … #define PLL1460X_MDIV_MASK … #define PLL46XX_PDIV_MASK … #define PLL46XX_SDIV_MASK … #define PLL46XX_VSEL_SHIFT … #define PLL46XX_MDIV_SHIFT … #define PLL46XX_PDIV_SHIFT … #define PLL46XX_SDIV_SHIFT … #define PLL46XX_KDIV_MASK … #define PLL4650C_KDIV_MASK … #define PLL46XX_KDIV_SHIFT … #define PLL46XX_MFR_MASK … #define PLL46XX_MRR_MASK … #define PLL46XX_KDIV_SHIFT … #define PLL46XX_MFR_SHIFT … #define PLL46XX_MRR_SHIFT … #define PLL46XX_ENABLE … #define PLL46XX_LOCKED … #define PLL46XX_VSEL … static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, const struct samsung_pll_rate_table *rate) { … } static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll46xx_clk_ops = …; static const struct clk_ops samsung_pll46xx_clk_min_ops = …; /* * PLL6552 Clock Type */ #define PLL6552_MDIV_MASK … #define PLL6552_PDIV_MASK … #define PLL6552_SDIV_MASK … #define PLL6552_MDIV_SHIFT … #define PLL6552_MDIV_SHIFT_2416 … #define PLL6552_PDIV_SHIFT … #define PLL6552_PDIV_SHIFT_2416 … #define PLL6552_SDIV_SHIFT … static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll6552_clk_ops = …; /* * PLL6553 Clock Type */ #define PLL6553_MDIV_MASK … #define PLL6553_PDIV_MASK … #define PLL6553_SDIV_MASK … #define PLL6553_KDIV_MASK … #define PLL6553_MDIV_SHIFT … #define PLL6553_PDIV_SHIFT … #define PLL6553_SDIV_SHIFT … #define PLL6553_KDIV_SHIFT … static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll6553_clk_ops = …; /* * PLL2550x Clock Type */ #define PLL2550X_R_MASK … #define PLL2550X_P_MASK … #define PLL2550X_M_MASK … #define PLL2550X_S_MASK … #define PLL2550X_R_SHIFT … #define PLL2550X_P_SHIFT … #define PLL2550X_M_SHIFT … #define PLL2550X_S_SHIFT … static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll2550x_clk_ops = …; /* * PLL2550xx Clock Type */ /* Maximum lock time can be 270 * PDIV cycles */ #define PLL2550XX_LOCK_FACTOR … #define PLL2550XX_M_MASK … #define PLL2550XX_P_MASK … #define PLL2550XX_S_MASK … #define PLL2550XX_LOCK_STAT_MASK … #define PLL2550XX_M_SHIFT … #define PLL2550XX_P_SHIFT … #define PLL2550XX_S_SHIFT … #define PLL2550XX_LOCK_STAT_SHIFT … static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) { … } static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll2550xx_clk_ops = …; static const struct clk_ops samsung_pll2550xx_clk_min_ops = …; /* * PLL2650x Clock Type */ /* Maximum lock time can be 3000 * PDIV cycles */ #define PLL2650X_LOCK_FACTOR … #define PLL2650X_M_MASK … #define PLL2650X_P_MASK … #define PLL2650X_S_MASK … #define PLL2650X_K_MASK … #define PLL2650X_LOCK_STAT_MASK … #define PLL2650X_M_SHIFT … #define PLL2650X_P_SHIFT … #define PLL2650X_S_SHIFT … #define PLL2650X_K_SHIFT … #define PLL2650X_LOCK_STAT_SHIFT … #define PLL2650X_PLL_ENABLE_SHIFT … static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static const struct clk_ops samsung_pll2650x_clk_ops = …; static const struct clk_ops samsung_pll2650x_clk_min_ops = …; /* * PLL2650XX Clock Type */ /* Maximum lock time can be 3000 * PDIV cycles */ #define PLL2650XX_LOCK_FACTOR … #define PLL2650XX_MDIV_SHIFT … #define PLL2650XX_PDIV_SHIFT … #define PLL2650XX_SDIV_SHIFT … #define PLL2650XX_KDIV_SHIFT … #define PLL2650XX_MDIV_MASK … #define PLL2650XX_PDIV_MASK … #define PLL2650XX_SDIV_MASK … #define PLL2650XX_KDIV_MASK … #define PLL2650XX_PLL_ENABLE_SHIFT … #define PLL2650XX_PLL_LOCKTIME_SHIFT … #define PLL2650XX_PLL_FOUTMASK_SHIFT … static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate) { … } static const struct clk_ops samsung_pll2650xx_clk_ops = …; static const struct clk_ops samsung_pll2650xx_clk_min_ops = …; static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_clk) { … } void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_list, unsigned int nr_pll) { … }
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