/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ #define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ /* LPASS Audio virtual ports IDs */ #define HDMI_RX … #define SLIMBUS_0_RX … #define SLIMBUS_0_TX … #define SLIMBUS_1_RX … #define SLIMBUS_1_TX … #define SLIMBUS_2_RX … #define SLIMBUS_2_TX … #define SLIMBUS_3_RX … #define SLIMBUS_3_TX … #define SLIMBUS_4_RX … #define SLIMBUS_4_TX … #define SLIMBUS_5_RX … #define SLIMBUS_5_TX … #define SLIMBUS_6_RX … #define SLIMBUS_6_TX … #define PRIMARY_MI2S_RX … #define PRIMARY_MI2S_TX … #define SECONDARY_MI2S_RX … #define SECONDARY_MI2S_TX … #define TERTIARY_MI2S_RX … #define TERTIARY_MI2S_TX … #define QUATERNARY_MI2S_RX … #define QUATERNARY_MI2S_TX … #define PRIMARY_TDM_RX_0 … #define PRIMARY_TDM_TX_0 … #define PRIMARY_TDM_RX_1 … #define PRIMARY_TDM_TX_1 … #define PRIMARY_TDM_RX_2 … #define PRIMARY_TDM_TX_2 … #define PRIMARY_TDM_RX_3 … #define PRIMARY_TDM_TX_3 … #define PRIMARY_TDM_RX_4 … #define PRIMARY_TDM_TX_4 … #define PRIMARY_TDM_RX_5 … #define PRIMARY_TDM_TX_5 … #define PRIMARY_TDM_RX_6 … #define PRIMARY_TDM_TX_6 … #define PRIMARY_TDM_RX_7 … #define PRIMARY_TDM_TX_7 … #define SECONDARY_TDM_RX_0 … #define SECONDARY_TDM_TX_0 … #define SECONDARY_TDM_RX_1 … #define SECONDARY_TDM_TX_1 … #define SECONDARY_TDM_RX_2 … #define SECONDARY_TDM_TX_2 … #define SECONDARY_TDM_RX_3 … #define SECONDARY_TDM_TX_3 … #define SECONDARY_TDM_RX_4 … #define SECONDARY_TDM_TX_4 … #define SECONDARY_TDM_RX_5 … #define SECONDARY_TDM_TX_5 … #define SECONDARY_TDM_RX_6 … #define SECONDARY_TDM_TX_6 … #define SECONDARY_TDM_RX_7 … #define SECONDARY_TDM_TX_7 … #define TERTIARY_TDM_RX_0 … #define TERTIARY_TDM_TX_0 … #define TERTIARY_TDM_RX_1 … #define TERTIARY_TDM_TX_1 … #define TERTIARY_TDM_RX_2 … #define TERTIARY_TDM_TX_2 … #define TERTIARY_TDM_RX_3 … #define TERTIARY_TDM_TX_3 … #define TERTIARY_TDM_RX_4 … #define TERTIARY_TDM_TX_4 … #define TERTIARY_TDM_RX_5 … #define TERTIARY_TDM_TX_5 … #define TERTIARY_TDM_RX_6 … #define TERTIARY_TDM_TX_6 … #define TERTIARY_TDM_RX_7 … #define TERTIARY_TDM_TX_7 … #define QUATERNARY_TDM_RX_0 … #define QUATERNARY_TDM_TX_0 … #define QUATERNARY_TDM_RX_1 … #define QUATERNARY_TDM_TX_1 … #define QUATERNARY_TDM_RX_2 … #define QUATERNARY_TDM_TX_2 … #define QUATERNARY_TDM_RX_3 … #define QUATERNARY_TDM_TX_3 … #define QUATERNARY_TDM_RX_4 … #define QUATERNARY_TDM_TX_4 … #define QUATERNARY_TDM_RX_5 … #define QUATERNARY_TDM_TX_5 … #define QUATERNARY_TDM_RX_6 … #define QUATERNARY_TDM_TX_6 … #define QUATERNARY_TDM_RX_7 … #define QUATERNARY_TDM_TX_7 … #define QUINARY_TDM_RX_0 … #define QUINARY_TDM_TX_0 … #define QUINARY_TDM_RX_1 … #define QUINARY_TDM_TX_1 … #define QUINARY_TDM_RX_2 … #define QUINARY_TDM_TX_2 … #define QUINARY_TDM_RX_3 … #define QUINARY_TDM_TX_3 … #define QUINARY_TDM_RX_4 … #define QUINARY_TDM_TX_4 … #define QUINARY_TDM_RX_5 … #define QUINARY_TDM_TX_5 … #define QUINARY_TDM_RX_6 … #define QUINARY_TDM_TX_6 … #define QUINARY_TDM_RX_7 … #define QUINARY_TDM_TX_7 … #define DISPLAY_PORT_RX … #define WSA_CODEC_DMA_RX_0 … #define WSA_CODEC_DMA_TX_0 … #define WSA_CODEC_DMA_RX_1 … #define WSA_CODEC_DMA_TX_1 … #define WSA_CODEC_DMA_TX_2 … #define VA_CODEC_DMA_TX_0 … #define VA_CODEC_DMA_TX_1 … #define VA_CODEC_DMA_TX_2 … #define RX_CODEC_DMA_RX_0 … #define TX_CODEC_DMA_TX_0 … #define RX_CODEC_DMA_RX_1 … #define TX_CODEC_DMA_TX_1 … #define RX_CODEC_DMA_RX_2 … #define TX_CODEC_DMA_TX_2 … #define RX_CODEC_DMA_RX_3 … #define TX_CODEC_DMA_TX_3 … #define RX_CODEC_DMA_RX_4 … #define TX_CODEC_DMA_TX_4 … #define RX_CODEC_DMA_RX_5 … #define TX_CODEC_DMA_TX_5 … #define RX_CODEC_DMA_RX_6 … #define RX_CODEC_DMA_RX_7 … #define QUINARY_MI2S_RX … #define QUINARY_MI2S_TX … #define DISPLAY_PORT_RX_0 … #define DISPLAY_PORT_RX_1 … #define DISPLAY_PORT_RX_2 … #define DISPLAY_PORT_RX_3 … #define DISPLAY_PORT_RX_4 … #define DISPLAY_PORT_RX_5 … #define DISPLAY_PORT_RX_6 … #define DISPLAY_PORT_RX_7 … #define LPASS_CLK_ID_PRI_MI2S_IBIT … #define LPASS_CLK_ID_PRI_MI2S_EBIT … #define LPASS_CLK_ID_SEC_MI2S_IBIT … #define LPASS_CLK_ID_SEC_MI2S_EBIT … #define LPASS_CLK_ID_TER_MI2S_IBIT … #define LPASS_CLK_ID_TER_MI2S_EBIT … #define LPASS_CLK_ID_QUAD_MI2S_IBIT … #define LPASS_CLK_ID_QUAD_MI2S_EBIT … #define LPASS_CLK_ID_SPEAKER_I2S_IBIT … #define LPASS_CLK_ID_SPEAKER_I2S_EBIT … #define LPASS_CLK_ID_SPEAKER_I2S_OSR … #define LPASS_CLK_ID_QUI_MI2S_IBIT … #define LPASS_CLK_ID_QUI_MI2S_EBIT … #define LPASS_CLK_ID_SEN_MI2S_IBIT … #define LPASS_CLK_ID_SEN_MI2S_EBIT … #define LPASS_CLK_ID_INT0_MI2S_IBIT … #define LPASS_CLK_ID_INT1_MI2S_IBIT … #define LPASS_CLK_ID_INT2_MI2S_IBIT … #define LPASS_CLK_ID_INT3_MI2S_IBIT … #define LPASS_CLK_ID_INT4_MI2S_IBIT … #define LPASS_CLK_ID_INT5_MI2S_IBIT … #define LPASS_CLK_ID_INT6_MI2S_IBIT … #define LPASS_CLK_ID_QUI_MI2S_OSR … #define LPASS_CLK_ID_PRI_PCM_IBIT … #define LPASS_CLK_ID_PRI_PCM_EBIT … #define LPASS_CLK_ID_SEC_PCM_IBIT … #define LPASS_CLK_ID_SEC_PCM_EBIT … #define LPASS_CLK_ID_TER_PCM_IBIT … #define LPASS_CLK_ID_TER_PCM_EBIT … #define LPASS_CLK_ID_QUAD_PCM_IBIT … #define LPASS_CLK_ID_QUAD_PCM_EBIT … #define LPASS_CLK_ID_QUIN_PCM_IBIT … #define LPASS_CLK_ID_QUIN_PCM_EBIT … #define LPASS_CLK_ID_QUI_PCM_OSR … #define LPASS_CLK_ID_PRI_TDM_IBIT … #define LPASS_CLK_ID_PRI_TDM_EBIT … #define LPASS_CLK_ID_SEC_TDM_IBIT … #define LPASS_CLK_ID_SEC_TDM_EBIT … #define LPASS_CLK_ID_TER_TDM_IBIT … #define LPASS_CLK_ID_TER_TDM_EBIT … #define LPASS_CLK_ID_QUAD_TDM_IBIT … #define LPASS_CLK_ID_QUAD_TDM_EBIT … #define LPASS_CLK_ID_QUIN_TDM_IBIT … #define LPASS_CLK_ID_QUIN_TDM_EBIT … #define LPASS_CLK_ID_QUIN_TDM_OSR … #define LPASS_CLK_ID_MCLK_1 … #define LPASS_CLK_ID_MCLK_2 … #define LPASS_CLK_ID_MCLK_3 … #define LPASS_CLK_ID_MCLK_4 … #define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE … #define LPASS_CLK_ID_INT_MCLK_0 … #define LPASS_CLK_ID_INT_MCLK_1 … #define LPASS_CLK_ID_MCLK_5 … #define LPASS_CLK_ID_WSA_CORE_MCLK … #define LPASS_CLK_ID_WSA_CORE_NPL_MCLK … #define LPASS_CLK_ID_VA_CORE_MCLK … #define LPASS_CLK_ID_TX_CORE_MCLK … #define LPASS_CLK_ID_TX_CORE_NPL_MCLK … #define LPASS_CLK_ID_RX_CORE_MCLK … #define LPASS_CLK_ID_RX_CORE_NPL_MCLK … #define LPASS_CLK_ID_VA_CORE_2X_MCLK … /* Clock ID for MCLK for WSA2 core */ #define LPASS_CLK_ID_WSA2_CORE_MCLK … /* Clock ID for NPL MCLK for WSA2 core */ #define LPASS_CLK_ID_WSA2_CORE_2X_MCLK … /* Clock ID for RX Core TX MCLK */ #define LPASS_CLK_ID_RX_CORE_TX_MCLK … /* Clock ID for RX CORE TX 2X MCLK */ #define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK … /* Clock ID for WSA core TX MCLK */ #define LPASS_CLK_ID_WSA_CORE_TX_MCLK … /* Clock ID for WSA core TX 2X MCLK */ #define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK … /* Clock ID for WSA2 core TX MCLK */ #define LPASS_CLK_ID_WSA2_CORE_TX_MCLK … /* Clock ID for WSA2 core TX 2X MCLK */ #define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK … /* Clock ID for RX CORE MCLK2 2X MCLK */ #define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK … #define LPASS_HW_AVTIMER_VOTE … #define LPASS_HW_MACRO_VOTE … #define LPASS_HW_DCODEC_VOTE … #define Q6AFE_MAX_CLK_ID … #define LPASS_CLK_ATTRIBUTE_INVALID … #define LPASS_CLK_ATTRIBUTE_COUPLE_NO … #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND … #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR … #endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */
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