/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __Q6PRM_H__ #define __Q6PRM_H__ /* Clock ID for Primary I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT … /* Clock ID for Primary I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT … /* Clock ID for Secondary I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT … /* Clock ID for Secondary I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT … /* Clock ID for Tertiary I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT … /* Clock ID for Tertiary I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT … /* Clock ID for Quartnery I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT … /* Clock ID for Quartnery I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT … /* Clock ID for Speaker I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT … /* Clock ID for Speaker I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT … /* Clock ID for Speaker I2S OSR */ #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR … /* Clock ID for QUINARY I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT … /* Clock ID for QUINARY I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT … /* Clock ID for SENARY I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT … /* Clock ID for SENARY I2S EBIT */ #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT … /* Clock ID for INT0 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT … /* Clock ID for INT1 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT … /* Clock ID for INT2 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT … /* Clock ID for INT3 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT … /* Clock ID for INT4 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT … /* Clock ID for INT5 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT … /* Clock ID for INT6 I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT … /* Clock ID for QUINARY MI2S OSR CLK */ #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR … #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK … #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK … #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK … #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK … #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK … #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK … #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK … #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK … /* Clock ID for MCLK for WSA2 core */ #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK … /* Clock ID for NPL MCLK for WSA2 core */ #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK … /* Clock ID for RX Core TX MCLK */ #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK … /* Clock ID for RX CORE TX 2X MCLK */ #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK … /* Clock ID for WSA core TX MCLK */ #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK … /* Clock ID for WSA core TX 2X MCLK */ #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK … /* Clock ID for WSA2 core TX MCLK */ #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK … /* Clock ID for WSA2 core TX 2X MCLK */ #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK … /* Clock ID for RX CORE MCLK2 2X MCLK */ #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK … #define Q6PRM_LPASS_CLK_SRC_INTERNAL … #define Q6PRM_LPASS_CLK_ROOT_DEFAULT … #define Q6PRM_HW_CORE_ID_LPASS … #define Q6PRM_HW_CORE_ID_DCODEC … int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, unsigned int freq); int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, const char *client_name, uint32_t *client_handle); int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle); #endif /* __Q6PRM_H__ */
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