linux/drivers/clk/samsung/clk-exynos5260.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 * Author: Rahul Sharma <[email protected]>
 *
 * Common Clock Framework support for Exynos5260 SoC.
 */

#include <linux/of.h>
#include <linux/of_address.h>

#include "clk-exynos5260.h"
#include "clk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/exynos5260-clk.h>

/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP
#define CLKS_NR_EGL
#define CLKS_NR_KFC
#define CLKS_NR_MIF
#define CLKS_NR_G3D
#define CLKS_NR_AUD
#define CLKS_NR_MFC
#define CLKS_NR_GSCL
#define CLKS_NR_FSYS
#define CLKS_NR_PERI
#define CLKS_NR_DISP
#define CLKS_NR_G2D
#define CLKS_NR_ISP

/*
 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
 */
static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst =;

/*
 * Applicable for 2650 Type PLL for AUD_PLL.
 */
static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst =;

/* CMU_AUD */

static const unsigned long aud_clk_regs[] __initconst =;

PNAME(mout_aud_pll_user_p) =;
PNAME(mout_sclk_aud_i2s_p) =;
PNAME(mout_sclk_aud_pcm_p) =;

static const struct samsung_mux_clock aud_mux_clks[] __initconst =;

static const struct samsung_div_clock aud_div_clks[] __initconst =;

static const struct samsung_gate_clock aud_gate_clks[] __initconst =;

static const struct samsung_cmu_info aud_cmu __initconst =;

static void __init exynos5260_clk_aud_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
		exynos5260_clk_aud_init);


/* CMU_DISP */

static const unsigned long disp_clk_regs[] __initconst =;

PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) =;
PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) =;
PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) =;
PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) =;
PNAME(mout_aclk_disp_222_user_p) =;
PNAME(mout_sclk_disp_pixel_user_p) =;
PNAME(mout_aclk_disp_333_user_p) =;
PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) =;
PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) =;
PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) =;
PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) =;
PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) =;
PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) =;
PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) =;
PNAME(mout_sclk_hdmi_pixel_p) =;
PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) =;
PNAME(mout_sclk_hdmi_spdif_p) =;

static const struct samsung_mux_clock disp_mux_clks[] __initconst =;

static const struct samsung_div_clock disp_div_clks[] __initconst =;

static const struct samsung_gate_clock disp_gate_clks[] __initconst =;

static const struct samsung_cmu_info disp_cmu __initconst =;

static void __init exynos5260_clk_disp_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
		exynos5260_clk_disp_init);


/* CMU_EGL */

static const unsigned long egl_clk_regs[] __initconst =;

PNAME(mout_egl_b_p) =;
PNAME(mout_egl_pll_p) =;

static const struct samsung_mux_clock egl_mux_clks[] __initconst =;

static const struct samsung_div_clock egl_div_clks[] __initconst =;

static const struct samsung_pll_clock egl_pll_clks[] __initconst =;

static const struct samsung_cmu_info egl_cmu __initconst =;

static void __init exynos5260_clk_egl_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
		exynos5260_clk_egl_init);


/* CMU_FSYS */

static const unsigned long fsys_clk_regs[] __initconst =;

PNAME(mout_phyclk_usbhost20_phyclk_user_p) =;
PNAME(mout_phyclk_usbhost20_freeclk_user_p) =;
PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) =;
PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) =;
PNAME(mout_phyclk_usbdrd30_phyclock_user_p) =;

static const struct samsung_mux_clock fsys_mux_clks[] __initconst =;

static const struct samsung_gate_clock fsys_gate_clks[] __initconst =;

static const struct samsung_cmu_info fsys_cmu __initconst =;

static void __init exynos5260_clk_fsys_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
		exynos5260_clk_fsys_init);


/* CMU_G2D */

static const unsigned long g2d_clk_regs[] __initconst =;

PNAME(mout_aclk_g2d_333_user_p) =;

static const struct samsung_mux_clock g2d_mux_clks[] __initconst =;

static const struct samsung_div_clock g2d_div_clks[] __initconst =;

static const struct samsung_gate_clock g2d_gate_clks[] __initconst =;

static const struct samsung_cmu_info g2d_cmu __initconst =;

static void __init exynos5260_clk_g2d_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
		exynos5260_clk_g2d_init);


/* CMU_G3D */

static const unsigned long g3d_clk_regs[] __initconst =;

PNAME(mout_g3d_pll_p) =;

static const struct samsung_mux_clock g3d_mux_clks[] __initconst =;

static const struct samsung_div_clock g3d_div_clks[] __initconst =;

static const struct samsung_gate_clock g3d_gate_clks[] __initconst =;

static const struct samsung_pll_clock g3d_pll_clks[] __initconst =;

static const struct samsung_cmu_info g3d_cmu __initconst =;

static void __init exynos5260_clk_g3d_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
		exynos5260_clk_g3d_init);


/* CMU_GSCL */

static const unsigned long gscl_clk_regs[] __initconst =;

PNAME(mout_aclk_gscl_333_user_p) =;
PNAME(mout_aclk_m2m_400_user_p) =;
PNAME(mout_aclk_gscl_fimc_user_p) =;
PNAME(mout_aclk_csis_p) =;

static const struct samsung_mux_clock gscl_mux_clks[] __initconst =;

static const struct samsung_div_clock gscl_div_clks[] __initconst =;

static const struct samsung_gate_clock gscl_gate_clks[] __initconst =;

static const struct samsung_cmu_info gscl_cmu __initconst =;

static void __init exynos5260_clk_gscl_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
		exynos5260_clk_gscl_init);


/* CMU_ISP */

static const unsigned long isp_clk_regs[] __initconst =;

PNAME(mout_isp_400_user_p) =;
PNAME(mout_isp_266_user_p)	 =;

static const struct samsung_mux_clock isp_mux_clks[] __initconst =;

static const struct samsung_div_clock isp_div_clks[] __initconst =;

static const struct samsung_gate_clock isp_gate_clks[] __initconst =;

static const struct samsung_cmu_info isp_cmu __initconst =;

static void __init exynos5260_clk_isp_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
		exynos5260_clk_isp_init);


/* CMU_KFC */

static const unsigned long kfc_clk_regs[] __initconst =;

PNAME(mout_kfc_pll_p) =;
PNAME(mout_kfc_p)	 =;

static const struct samsung_mux_clock kfc_mux_clks[] __initconst =;

static const struct samsung_div_clock kfc_div_clks[] __initconst =;

static const struct samsung_pll_clock kfc_pll_clks[] __initconst =;

static const struct samsung_cmu_info kfc_cmu __initconst =;

static void __init exynos5260_clk_kfc_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
		exynos5260_clk_kfc_init);


/* CMU_MFC */

static const unsigned long mfc_clk_regs[] __initconst =;

PNAME(mout_aclk_mfc_333_user_p) =;

static const struct samsung_mux_clock mfc_mux_clks[] __initconst =;

static const struct samsung_div_clock mfc_div_clks[] __initconst =;

static const struct samsung_gate_clock mfc_gate_clks[] __initconst =;

static const struct samsung_cmu_info mfc_cmu __initconst =;

static void __init exynos5260_clk_mfc_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
		exynos5260_clk_mfc_init);


/* CMU_MIF */

static const unsigned long mif_clk_regs[] __initconst =;

PNAME(mout_mem_pll_p) =;
PNAME(mout_bus_pll_p) =;
PNAME(mout_media_pll_p) =;
PNAME(mout_mif_drex_p) =;
PNAME(mout_mif_drex2x_p) =;
PNAME(mout_clkm_phy_p) =;
PNAME(mout_clk2x_phy_p) =;

static const struct samsung_mux_clock mif_mux_clks[] __initconst =;

static const struct samsung_div_clock mif_div_clks[] __initconst =;

static const struct samsung_gate_clock mif_gate_clks[] __initconst =;

static const struct samsung_pll_clock mif_pll_clks[] __initconst =;

static const struct samsung_cmu_info mif_cmu __initconst =;

static void __init exynos5260_clk_mif_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
		exynos5260_clk_mif_init);


/* CMU_PERI */

static const unsigned long peri_clk_regs[] __initconst =;

PNAME(mout_sclk_pcm_p) =;
PNAME(mout_sclk_i2scod_p) =;
PNAME(mout_sclk_spdif_p) =;

static const struct samsung_mux_clock peri_mux_clks[] __initconst =;

static const struct samsung_div_clock peri_div_clks[] __initconst =;

static const struct samsung_gate_clock peri_gate_clks[] __initconst =;

static const struct samsung_cmu_info peri_cmu __initconst =;

static void __init exynos5260_clk_peri_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
		exynos5260_clk_peri_init);


/* CMU_TOP */

static const unsigned long top_clk_regs[] __initconst =;

/* fixed rate clocks generated inside the soc */
static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst =;

PNAME(mout_memtop_pll_user_p) =;
PNAME(mout_bustop_pll_user_p) =;
PNAME(mout_mediatop_pll_user_p) =;
PNAME(mout_audtop_pll_user_p) =;
PNAME(mout_aud_pll_p) =;
PNAME(mout_disp_pll_p) =;
PNAME(mout_mfc_bustop_333_p) =;
PNAME(mout_aclk_mfc_333_p) =;
PNAME(mout_g2d_bustop_333_p) =;
PNAME(mout_aclk_g2d_333_p) =;
PNAME(mout_gscl_bustop_333_p) =;
PNAME(mout_aclk_gscl_333_p) =;
PNAME(mout_m2m_mediatop_400_p) =;
PNAME(mout_aclk_gscl_400_p) =;
PNAME(mout_gscl_bustop_fimc_p) =;
PNAME(mout_aclk_gscl_fimc_p) =;
PNAME(mout_isp1_media_266_p) =;
PNAME(mout_aclk_isp1_266_p) =;
PNAME(mout_isp1_media_400_p) =;
PNAME(mout_aclk_isp1_400_p) =;
PNAME(mout_sclk_isp_spi_p) =;
PNAME(mout_sclk_isp_uart_p) =;
PNAME(mout_sclk_isp_sensor_p) =;
PNAME(mout_disp_disp_333_p) =;
PNAME(mout_aclk_disp_333_p) =;
PNAME(mout_disp_disp_222_p) =;
PNAME(mout_aclk_disp_222_p) =;
PNAME(mout_disp_media_pixel_p) =;
PNAME(mout_sclk_disp_pixel_p) =;
PNAME(mout_bus_bustop_400_p) =;
PNAME(mout_bus_bustop_100_p) =;
PNAME(mout_sclk_peri_spi_clk_p) =;
PNAME(mout_sclk_peri_uart_uclk_p) =;
PNAME(mout_sclk_fsys_usb_p) =;
PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) =;
PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) =;
PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) =;
PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) =;

static const struct samsung_mux_clock top_mux_clks[] __initconst =;

static const struct samsung_div_clock top_div_clks[] __initconst =;

static const struct samsung_gate_clock top_gate_clks[] __initconst =;

static const struct samsung_pll_clock top_pll_clks[] __initconst =;

static const struct samsung_cmu_info top_cmu __initconst =;

static void __init exynos5260_clk_top_init(struct device_node *np)
{}

CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
		exynos5260_clk_top_init);