/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. * * Author: Ajit Kumar Pandey <[email protected]> */ #ifndef _ACP_DSP_IP_OFFSET_H #define _ACP_DSP_IP_OFFSET_H /* Registers from ACP_DMA_0 block */ #define ACP_DMA_CNTL_0 … #define ACP_DMA_DSCR_STRT_IDX_0 … #define ACP_DMA_DSCR_CNT_0 … #define ACP_DMA_PRIO_0 … #define ACP_DMA_CUR_DSCR_0 … #define ACP_DMA_ERR_STS_0 … #define ACP_DMA_DESC_BASE_ADDR … #define ACP_DMA_DESC_MAX_NUM_DSCR … #define ACP_DMA_CH_STS … #define ACP_DMA_CH_GROUP … #define ACP_DMA_CH_RST_STS … /* Registers from ACP_DSP_0 block */ #define ACP_DSP0_RUNSTALL … /* Registers from ACP_AXI2AXIATU block */ #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 … #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 … #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 … #define ACPAXI2AXI_ATU_CTRL … #define ACP_SOFT_RESET … #define ACP_CONTROL … #define ACP3X_I2S_PIN_CONFIG … #define ACP5X_I2S_PIN_CONFIG … #define ACP6X_I2S_PIN_CONFIG … /* Registers offsets from ACP_PGFSM block */ #define ACP3X_PGFSM_BASE … #define ACP5X_PGFSM_BASE … #define ACP6X_PGFSM_BASE … #define PGFSM_CONTROL_OFFSET … #define PGFSM_STATUS_OFFSET … #define ACP3X_CLKMUX_SEL … #define ACP5X_CLKMUX_SEL … #define ACP6X_CLKMUX_SEL … /* Registers from ACP_INTR block */ #define ACP3X_EXT_INTR_STAT … #define ACP5X_EXT_INTR_STAT … #define ACP6X_EXTERNAL_INTR_ENB … #define ACP6X_EXTERNAL_INTR_CNTL … #define ACP6X_EXT_INTR_STAT … #define ACP6X_EXT_INTR_STAT1 … #define ACP3X_DSP_SW_INTR_BASE … #define ACP5X_DSP_SW_INTR_BASE … #define ACP6X_DSP_SW_INTR_BASE … #define DSP_SW_INTR_CNTL_OFFSET … #define DSP_SW_INTR_STAT_OFFSET … #define DSP_SW_INTR_TRIG_OFFSET … #define ACP_ERROR_STATUS … #define ACP3X_AXI2DAGB_SEM_0 … #define ACP5X_AXI2DAGB_SEM_0 … #define ACP6X_AXI2DAGB_SEM_0 … /* ACP common registers to report errors related to I2S & SoundWire interfaces */ #define ACP_SW0_I2S_ERROR_REASON … #define ACP_SW1_I2S_ERROR_REASON … /* Registers from ACP_SHA block */ #define ACP_SHA_DSP_FW_QUALIFIER … #define ACP_SHA_DMA_CMD … #define ACP_SHA_MSG_LENGTH … #define ACP_SHA_DMA_STRT_ADDR … #define ACP_SHA_DMA_DESTINATION_ADDR … #define ACP_SHA_DMA_CMD_STS … #define ACP_SHA_DMA_ERR_STATUS … #define ACP_SHA_TRANSFER_BYTE_CNT … #define ACP_SHA_DMA_INCLUDE_HDR … #define ACP_SHA_PSP_ACK … #define ACP_SCRATCH_REG_0 … #define ACP6X_DSP_FUSION_RUNSTALL … /* Cache window registers */ #define ACP_DSP0_CACHE_OFFSET0 … #define ACP_DSP0_CACHE_SIZE0 … #define ACP_SW0_EN … #define ACP_SW1_EN … #endif
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