/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2022 Intel Corporation */ #ifndef __IPC4_FW_REG_H__ #define __IPC4_FW_REG_H__ #define SOF_IPC4_INVALID_STREAM_POSITION … /** * struct sof_ipc4_pipeline_registers - Pipeline start and end information in fw * @stream_start_offset: Stream start offset (LPIB) reported by mixin * module allocated on pipeline attached to Host Output Gateway when * first data is being mixed to mixout module. When data is not mixed * (right after creation/after reset) value "(u64)-1" is reported * @stream_end_offset: Stream end offset (LPIB) reported by mixin * module allocated on pipeline attached to Host Output Gateway * during transition from RUNNING to PAUSED. When data is not mixed * (right after creation or after reset) value "(u64)-1" is reported. * When first data is mixed then value "0"is reported. */ struct sof_ipc4_pipeline_registers { … } __packed __aligned(…); #define SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS … /** * struct sof_ipc4_peak_volume_regs - Volume information in fw * @peak_meter: Peak volume value in fw * @current_volume: Current volume value in fw * @target_volume: Target volume value in fw */ struct sof_ipc4_peak_volume_regs { … } __packed __aligned(…); /** * struct sof_ipc4_llp_reading - Llp information in fw * @llp_l: Lower part of 64-bit LLP * @llp_u: Upper part of 64-bit LLP * @wclk_l: Lower part of 64-bit Wallclock * @wclk_u: Upper part of 64-bit Wallclock */ struct sof_ipc4_llp_reading { … } __packed __aligned(…); /** * struct of sof_ipc4_llp_reading_extended - Extended llp info * @llp_reading: Llp information in memory window * @tpd_low: Total processed data (low part) * @tpd_high: Total processed data (high part) */ struct sof_ipc4_llp_reading_extended { … } __packed __aligned(…); /** * struct sof_ipc4_llp_reading_slot - Llp slot information in memory window * @node_id: Dai gateway node id * @reading: Llp information in memory window */ struct sof_ipc4_llp_reading_slot { … } __packed __aligned(…); /* ROM information */ #define SOF_IPC4_FW_FUSE_VALUE_MASK … #define SOF_IPC4_FW_LOAD_METHOD_MASK … #define SOF_IPC4_FW_DOWNLINK_IPC_USE_DMA_MASK … #define SOF_IPC4_FW_LOAD_METHOD_REV_MASK … #define SOF_IPC4_FW_REVISION_MIN_MASK … #define SOF_IPC4_FW_REVISION_MAJ_MASK … #define SOF_IPC4_FW_VERSION_MIN_MASK … #define SOF_IPC4_FW_VERSION_MAJ_MASK … /* Number of dsp core supported in FW Regs. */ #define SOF_IPC4_MAX_SUPPORTED_ADSP_CORES … /* Number of host pipeline registers slots in FW Regs. */ #define SOF_IPC4_MAX_PIPELINE_REG_SLOTS … /* Number of PeakVol registers slots in FW Regs. */ #define SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS … /* Number of GPDMA LLP Reading slots in FW Regs. */ #define SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS … /* Number of Aggregated SNDW Reading slots in FW Regs. */ #define SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS … /* Current ABI version of the Fw registers layout. */ #define SOF_IPC4_FW_REGS_ABI_VER … /** * struct sof_ipc4_fw_registers - FW Registers exposes additional * DSP / FW state information to the driver * @fw_status: Current ROM / FW status * @lec: Last ROM / FW error code * @fps: Current DSP clock status * @lnec: Last Native Error Code(from external library) * @ltr: Copy of LTRC HW register value(FW only) * @rsvd0: Reserved0 * @rom_info: ROM info * @abi_ver: Version of the layout, set to the current FW_REGS_ABI_VER * @slave_core_sts: Slave core states * @rsvd2: Reserved2 * @pipeline_regs: State of pipelines attached to host output gateways * @peak_vol_regs: State of PeakVol instances indexed by the PeakVol's instance_id * @llp_gpdma_reading_slots: LLP Readings for single link gateways * @llp_sndw_reading_slots: SNDW aggregated link gateways * @llp_evad_reading_slot: LLP Readings for EVAD gateway */ struct sof_ipc4_fw_registers { … } __packed __aligned(…); #endif
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