/* SPDX-License-Identifier: GPL-2.0-only */ /* * STM32 ALSA SoC Digital Audio Interface (SAI) driver. * * Copyright (C) 2016, STMicroelectronics - All Rights Reserved * Author(s): Olivier Moysan <[email protected]> for STMicroelectronics. */ #include <linux/bitfield.h> /******************** SAI Register Map **************************************/ /* Global configuration register */ #define STM_SAI_GCR … /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ #define STM_SAI_CR1_REGX … #define STM_SAI_CR2_REGX … #define STM_SAI_FRCR_REGX … #define STM_SAI_SLOTR_REGX … #define STM_SAI_IMR_REGX … #define STM_SAI_SR_REGX … #define STM_SAI_CLRFR_REGX … #define STM_SAI_DR_REGX … /* Sub-block A registers, relative to sub-block A address */ #define STM_SAI_PDMCR_REGX … #define STM_SAI_PDMLY_REGX … /* Hardware configuration registers */ #define STM_SAI_HWCFGR … #define STM_SAI_VERR … #define STM_SAI_IDR … #define STM_SAI_SIDR … /******************** Bit definition for SAI_GCR register *******************/ #define SAI_GCR_SYNCIN_SHIFT … #define SAI_GCR_SYNCIN_WDTH … #define SAI_GCR_SYNCIN_MASK … #define SAI_GCR_SYNCIN_MAX … #define SAI_GCR_SYNCOUT_SHIFT … #define SAI_GCR_SYNCOUT_MASK … /******************* Bit definition for SAI_XCR1 register *******************/ #define SAI_XCR1_RX_TX_SHIFT … #define SAI_XCR1_RX_TX … #define SAI_XCR1_SLAVE_SHIFT … #define SAI_XCR1_SLAVE … #define SAI_XCR1_PRTCFG_SHIFT … #define SAI_XCR1_PRTCFG_MASK … #define SAI_XCR1_PRTCFG_SET(x) … #define SAI_XCR1_DS_SHIFT … #define SAI_XCR1_DS_MASK … #define SAI_XCR1_DS_SET(x) … #define SAI_XCR1_LSBFIRST_SHIFT … #define SAI_XCR1_LSBFIRST … #define SAI_XCR1_CKSTR_SHIFT … #define SAI_XCR1_CKSTR … #define SAI_XCR1_SYNCEN_SHIFT … #define SAI_XCR1_SYNCEN_MASK … #define SAI_XCR1_SYNCEN_SET(x) … #define SAI_XCR1_MONO_SHIFT … #define SAI_XCR1_MONO … #define SAI_XCR1_OUTDRIV_SHIFT … #define SAI_XCR1_OUTDRIV … #define SAI_XCR1_SAIEN_SHIFT … #define SAI_XCR1_SAIEN … #define SAI_XCR1_DMAEN_SHIFT … #define SAI_XCR1_DMAEN … #define SAI_XCR1_NODIV_SHIFT … #define SAI_XCR1_NODIV … #define SAI_XCR1_MCKDIV_SHIFT … #define SAI_XCR1_MCKDIV_WIDTH(x) … #define SAI_XCR1_MCKDIV_MASK(x) … #define SAI_XCR1_MCKDIV_SET(x) … #define SAI_XCR1_MCKDIV_MAX(x) … #define SAI_XCR1_OSR_SHIFT … #define SAI_XCR1_OSR … #define SAI_XCR1_MCKEN_SHIFT … #define SAI_XCR1_MCKEN … /******************* Bit definition for SAI_XCR2 register *******************/ #define SAI_XCR2_FTH_SHIFT … #define SAI_XCR2_FTH_MASK … #define SAI_XCR2_FTH_SET(x) … #define SAI_XCR2_FFLUSH_SHIFT … #define SAI_XCR2_FFLUSH … #define SAI_XCR2_TRIS_SHIFT … #define SAI_XCR2_TRIS … #define SAI_XCR2_MUTE_SHIFT … #define SAI_XCR2_MUTE … #define SAI_XCR2_MUTEVAL_SHIFT … #define SAI_XCR2_MUTEVAL … #define SAI_XCR2_MUTECNT_SHIFT … #define SAI_XCR2_MUTECNT_MASK … #define SAI_XCR2_MUTECNT_SET(x) … #define SAI_XCR2_CPL_SHIFT … #define SAI_XCR2_CPL … #define SAI_XCR2_COMP_SHIFT … #define SAI_XCR2_COMP_MASK … #define SAI_XCR2_COMP_SET(x) … /****************** Bit definition for SAI_XFRCR register *******************/ #define SAI_XFRCR_FRL_SHIFT … #define SAI_XFRCR_FRL_MASK … #define SAI_XFRCR_FRL_SET(x) … #define SAI_XFRCR_FSALL_SHIFT … #define SAI_XFRCR_FSALL_MASK … #define SAI_XFRCR_FSALL_SET(x) … #define SAI_XFRCR_FSDEF_SHIFT … #define SAI_XFRCR_FSDEF … #define SAI_XFRCR_FSPOL_SHIFT … #define SAI_XFRCR_FSPOL … #define SAI_XFRCR_FSOFF_SHIFT … #define SAI_XFRCR_FSOFF … /****************** Bit definition for SAI_XSLOTR register ******************/ #define SAI_XSLOTR_FBOFF_SHIFT … #define SAI_XSLOTR_FBOFF_MASK … #define SAI_XSLOTR_FBOFF_SET(x) … #define SAI_XSLOTR_SLOTSZ_SHIFT … #define SAI_XSLOTR_SLOTSZ_MASK … #define SAI_XSLOTR_SLOTSZ_SET(x) … #define SAI_XSLOTR_NBSLOT_SHIFT … #define SAI_XSLOTR_NBSLOT_MASK … #define SAI_XSLOTR_NBSLOT_SET(x) … #define SAI_XSLOTR_SLOTEN_SHIFT … #define SAI_XSLOTR_SLOTEN_WIDTH … #define SAI_XSLOTR_SLOTEN_MASK … #define SAI_XSLOTR_SLOTEN_SET(x) … /******************* Bit definition for SAI_XIMR register *******************/ #define SAI_XIMR_OVRUDRIE … #define SAI_XIMR_MUTEDETIE … #define SAI_XIMR_WCKCFGIE … #define SAI_XIMR_FREQIE … #define SAI_XIMR_CNRDYIE … #define SAI_XIMR_AFSDETIE … #define SAI_XIMR_LFSDETIE … #define SAI_XIMR_SHIFT … #define SAI_XIMR_MASK … /******************** Bit definition for SAI_XSR register *******************/ #define SAI_XSR_OVRUDR … #define SAI_XSR_MUTEDET … #define SAI_XSR_WCKCFG … #define SAI_XSR_FREQ … #define SAI_XSR_CNRDY … #define SAI_XSR_AFSDET … #define SAI_XSR_LFSDET … #define SAI_XSR_SHIFT … #define SAI_XSR_MASK … /****************** Bit definition for SAI_XCLRFR register ******************/ #define SAI_XCLRFR_COVRUDR … #define SAI_XCLRFR_CMUTEDET … #define SAI_XCLRFR_CWCKCFG … #define SAI_XCLRFR_CFREQ … #define SAI_XCLRFR_CCNRDY … #define SAI_XCLRFR_CAFSDET … #define SAI_XCLRFR_CLFSDET … #define SAI_XCLRFR_SHIFT … #define SAI_XCLRFR_MASK … /****************** Bit definition for SAI_PDMCR register ******************/ #define SAI_PDMCR_PDMEN … #define SAI_PDMCR_MICNBR_SHIFT … #define SAI_PDMCR_MICNBR_MASK … #define SAI_PDMCR_MICNBR_SET(x) … #define SAI_PDMCR_CKEN1 … #define SAI_PDMCR_CKEN2 … #define SAI_PDMCR_CKEN3 … #define SAI_PDMCR_CKEN4 … /****************** Bit definition for (SAI_PDMDLY register ****************/ #define SAI_PDMDLY_1L_SHIFT … #define SAI_PDMDLY_1L_MASK … #define SAI_PDMDLY_1L_WIDTH … #define SAI_PDMDLY_1R_SHIFT … #define SAI_PDMDLY_1R_MASK … #define SAI_PDMDLY_1R_WIDTH … #define SAI_PDMDLY_2L_SHIFT … #define SAI_PDMDLY_2L_MASK … #define SAI_PDMDLY_2L_WIDTH … #define SAI_PDMDLY_2R_SHIFT … #define SAI_PDMDLY_2R_MASK … #define SAI_PDMDLY_2R_WIDTH … #define SAI_PDMDLY_3L_SHIFT … #define SAI_PDMDLY_3L_MASK … #define SAI_PDMDLY_3L_WIDTH … #define SAI_PDMDLY_3R_SHIFT … #define SAI_PDMDLY_3R_MASK … #define SAI_PDMDLY_3R_WIDTH … #define SAI_PDMDLY_4L_SHIFT … #define SAI_PDMDLY_4L_MASK … #define SAI_PDMDLY_4L_WIDTH … #define SAI_PDMDLY_4R_SHIFT … #define SAI_PDMDLY_4R_MASK … #define SAI_PDMDLY_4R_WIDTH … /* Registers below apply to SAI version 2.1 and more */ /* Bit definition for SAI_HWCFGR register */ #define SAI_HWCFGR_FIFO_SIZE … #define SAI_HWCFGR_SPDIF_PDM … #define SAI_HWCFGR_REGOUT … /* Bit definition for SAI_VERR register */ #define SAI_VERR_MIN_MASK … #define SAI_VERR_MAJ_MASK … /* Bit definition for SAI_IDR register */ #define SAI_IDR_ID_MASK … /* Bit definition for SAI_SIDR register */ #define SAI_SIDR_ID_MASK … #define SAI_IPIDR_NUMBER … /* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */ #define STM_SAI_STM32F4 … /* Dummy version number for H7 socs and next */ #define STM_SAI_STM32H7 … #define STM_SAI_IS_F4(ip) … #define STM_SAI_HAS_SPDIF_PDM(ip) … enum stm32_sai_syncout { … }; /** * struct stm32_sai_conf - SAI configuration * @version: SAI version * @fifo_size: SAI fifo size as words number * @has_spdif_pdm: SAI S/PDIF and PDM features support flag */ struct stm32_sai_conf { … }; /** * struct stm32_sai_data - private data of SAI instance driver * @pdev: device data pointer * @base: common register bank virtual base address * @pclk: SAI bus clock * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz * @conf: SAI hardware capabitilites * @irq: SAI interrupt line * @set_sync: pointer to synchro mode configuration callback * @gcr: SAI Global Configuration Register */ struct stm32_sai_data { … };
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