/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver * * Copyright (c) 2012 Lucas Stach <[email protected]> * * Partly based on code copyright/by: * * Copyright (c) 2011,2012 Toradex Inc. */ #ifndef __TEGRA20_AC97_H__ #define __TEGRA20_AC97_H__ #include "tegra_pcm.h" #define TEGRA20_AC97_CTRL … #define TEGRA20_AC97_CMD … #define TEGRA20_AC97_STATUS1 … /* ... */ #define TEGRA20_AC97_FIFO1_SCR … /* ... */ #define TEGRA20_AC97_FIFO_TX1 … #define TEGRA20_AC97_FIFO_RX1 … /* TEGRA20_AC97_CTRL */ #define TEGRA20_AC97_CTRL_STM2_EN … #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN … #define TEGRA20_AC97_CTRL_IO_CNTRL_EN … #define TEGRA20_AC97_CTRL_HSET_DAC_EN … #define TEGRA20_AC97_CTRL_LINE2_DAC_EN … #define TEGRA20_AC97_CTRL_PCM_LFE_EN … #define TEGRA20_AC97_CTRL_PCM_SUR_EN … #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN … #define TEGRA20_AC97_CTRL_LINE1_DAC_EN … #define TEGRA20_AC97_CTRL_PCM_DAC_EN … #define TEGRA20_AC97_CTRL_COLD_RESET … #define TEGRA20_AC97_CTRL_WARM_RESET … #define TEGRA20_AC97_CTRL_STM_EN … /* TEGRA20_AC97_CMD */ #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT … #define TEGRA20_AC97_CMD_CMD_ADDR_MASK … #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT … #define TEGRA20_AC97_CMD_CMD_DATA_MASK … #define TEGRA20_AC97_CMD_CMD_ID_SHIFT … #define TEGRA20_AC97_CMD_CMD_ID_MASK … #define TEGRA20_AC97_CMD_BUSY … /* TEGRA20_AC97_STATUS1 */ #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT … #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK … #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT … #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK … #define TEGRA20_AC97_STATUS1_STA_VALID1 … #define TEGRA20_AC97_STATUS1_STANDBY1 … #define TEGRA20_AC97_STATUS1_CODEC1_RDY … /* TEGRA20_AC97_FIFO1_SCR */ #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT … #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK … #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT … #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK … #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA … #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA … #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT … #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT … #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN … #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN … #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN … #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN … #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN … #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN … #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN … #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN … struct tegra20_ac97 { … }; #endif /* __TEGRA20_AC97_H__ */
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