/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver * * Author: Stephen Warren <[email protected]> * Copyright (C) 2011 - NVIDIA, Inc. * * Based on code copyright/by: * Copyright (c) 2008-2009, NVIDIA Corporation */ #ifndef __TEGRA20_SPDIF_H__ #define __TEGRA20_SPDIF_H__ #include "tegra_pcm.h" /* Offsets from TEGRA20_SPDIF_BASE */ #define TEGRA20_SPDIF_CTRL … #define TEGRA20_SPDIF_STATUS … #define TEGRA20_SPDIF_STROBE_CTRL … #define TEGRA20_SPDIF_DATA_FIFO_CSR … #define TEGRA20_SPDIF_DATA_OUT … #define TEGRA20_SPDIF_DATA_IN … #define TEGRA20_SPDIF_CH_STA_RX_A … #define TEGRA20_SPDIF_CH_STA_RX_B … #define TEGRA20_SPDIF_CH_STA_RX_C … #define TEGRA20_SPDIF_CH_STA_RX_D … #define TEGRA20_SPDIF_CH_STA_RX_E … #define TEGRA20_SPDIF_CH_STA_RX_F … #define TEGRA20_SPDIF_CH_STA_TX_A … #define TEGRA20_SPDIF_CH_STA_TX_B … #define TEGRA20_SPDIF_CH_STA_TX_C … #define TEGRA20_SPDIF_CH_STA_TX_D … #define TEGRA20_SPDIF_CH_STA_TX_E … #define TEGRA20_SPDIF_CH_STA_TX_F … #define TEGRA20_SPDIF_USR_STA_RX_A … #define TEGRA20_SPDIF_USR_DAT_TX_A … /* Fields in TEGRA20_SPDIF_CTRL */ /* Start capturing from 0=right, 1=left channel */ #define TEGRA20_SPDIF_CTRL_CAP_LC … /* SPDIF receiver(RX) enable */ #define TEGRA20_SPDIF_CTRL_RX_EN … /* SPDIF Transmitter(TX) enable */ #define TEGRA20_SPDIF_CTRL_TX_EN … /* Transmit Channel status */ #define TEGRA20_SPDIF_CTRL_TC_EN … /* Transmit user Data */ #define TEGRA20_SPDIF_CTRL_TU_EN … /* Interrupt on transmit error */ #define TEGRA20_SPDIF_CTRL_IE_TXE … /* Interrupt on receive error */ #define TEGRA20_SPDIF_CTRL_IE_RXE … /* Interrupt on invalid preamble */ #define TEGRA20_SPDIF_CTRL_IE_P … /* Interrupt on "B" preamble */ #define TEGRA20_SPDIF_CTRL_IE_B … /* Interrupt when block of channel status received */ #define TEGRA20_SPDIF_CTRL_IE_C … /* Interrupt when a valid information unit (IU) is received */ #define TEGRA20_SPDIF_CTRL_IE_U … /* Interrupt when RX user FIFO attention level is reached */ #define TEGRA20_SPDIF_CTRL_QE_RU … /* Interrupt when TX user FIFO attention level is reached */ #define TEGRA20_SPDIF_CTRL_QE_TU … /* Interrupt when RX data FIFO attention level is reached */ #define TEGRA20_SPDIF_CTRL_QE_RX … /* Interrupt when TX data FIFO attention level is reached */ #define TEGRA20_SPDIF_CTRL_QE_TX … /* Loopback test mode enable */ #define TEGRA20_SPDIF_CTRL_LBK_EN … /* * Pack data mode: * 0 = Single data (16 bit needs to be padded to match the * interface data bit size). * 1 = Packeted left/right channel data into a single word. */ #define TEGRA20_SPDIF_CTRL_PACK … /* * 00 = 16bit data * 01 = 20bit data * 10 = 24bit data * 11 = raw data */ #define TEGRA20_SPDIF_BIT_MODE_16BIT … #define TEGRA20_SPDIF_BIT_MODE_20BIT … #define TEGRA20_SPDIF_BIT_MODE_24BIT … #define TEGRA20_SPDIF_BIT_MODE_RAW … #define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT … #define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK … #define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT … #define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT … #define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT … #define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW … /* Fields in TEGRA20_SPDIF_STATUS */ /* * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must * write a 1 to the corresponding bit location to clear the status. */ /* * Receiver(RX) shifter is busy receiving data. * This bit is asserted when the receiver first locked onto the * preamble of the data stream after RX_EN is asserted. This bit is * deasserted when either, * (a) the end of a frame is reached after RX_EN is deeasserted, or * (b) the SPDIF data stream becomes inactive. */ #define TEGRA20_SPDIF_STATUS_RX_BSY … /* * Transmitter(TX) shifter is busy transmitting data. * This bit is asserted when TX_EN is asserted. * This bit is deasserted when the end of a frame is reached after * TX_EN is deasserted. */ #define TEGRA20_SPDIF_STATUS_TX_BSY … /* * TX is busy shifting out channel status. * This bit is asserted when both TX_EN and TC_EN are asserted and * data from CH_STA_TX_A register is loaded into the internal shifter. * This bit is deasserted when either, * (a) the end of a frame is reached after TX_EN is deasserted, or * (b) CH_STA_TX_F register is loaded into the internal shifter. */ #define TEGRA20_SPDIF_STATUS_TC_BSY … /* * TX User data FIFO busy. * This bit is asserted when TX_EN and TXU_EN are asserted and * there's data in the TX user FIFO. This bit is deassert when either, * (a) the end of a frame is reached after TX_EN is deasserted, or * (b) there's no data left in the TX user FIFO. */ #define TEGRA20_SPDIF_STATUS_TU_BSY … /* TX FIFO Underrun error status */ #define TEGRA20_SPDIF_STATUS_TX_ERR … /* RX FIFO Overrun error status */ #define TEGRA20_SPDIF_STATUS_RX_ERR … /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */ #define TEGRA20_SPDIF_STATUS_IS_P … /* B-preamble detection status: 0=not detected, 1=B-preamble detected */ #define TEGRA20_SPDIF_STATUS_IS_B … /* * RX channel block data receive status: * 0=entire block not recieved yet. * 1=received entire block of channel status, */ #define TEGRA20_SPDIF_STATUS_IS_C … /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ #define TEGRA20_SPDIF_STATUS_IS_U … /* * RX User FIFO Status: * 1=attention level reached, 0=attention level not reached. */ #define TEGRA20_SPDIF_STATUS_QS_RU … /* * TX User FIFO Status: * 1=attention level reached, 0=attention level not reached. */ #define TEGRA20_SPDIF_STATUS_QS_TU … /* * RX Data FIFO Status: * 1=attention level reached, 0=attention level not reached. */ #define TEGRA20_SPDIF_STATUS_QS_RX … /* * TX Data FIFO Status: * 1=attention level reached, 0=attention level not reached. */ #define TEGRA20_SPDIF_STATUS_QS_TX … /* Fields in TEGRA20_SPDIF_STROBE_CTRL */ /* * Indicates the approximate number of detected SPDIFIN clocks within a * bi-phase period. */ #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT … #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK … /* Data strobe mode: 0=Auto-locked 1=Manual locked */ #define TEGRA20_SPDIF_STROBE_CTRL_STROBE … /* * Manual data strobe time within the bi-phase clock period (in terms of * the number of over-sampling clocks). */ #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT … #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK … /* * Manual SPDIFIN bi-phase clock period (in terms of the number of * over-sampling clocks). */ #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT … #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK … /* Fields in SPDIF_DATA_FIFO_CSR */ /* Clear Receiver User FIFO (RX USR.FIFO) */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR … #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT … #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS … #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS … #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS … /* RU FIFO attention level */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL … /* Number of RX USR.FIFO levels with valid data. */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK … /* Clear Transmitter User FIFO (TX USR.FIFO) */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR … /* TU FIFO attention level */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL … /* Number of TX USR.FIFO levels that could be filled. */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK … /* Clear Receiver Data FIFO (RX DATA.FIFO) */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR … #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT … #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS … #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS … #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS … /* RU FIFO attention level */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL … /* Number of RX DATA.FIFO levels with valid data. */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK … /* Clear Transmitter Data FIFO (TX DATA.FIFO) */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR … /* TU FIFO attention level */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL … /* Number of TX DATA.FIFO levels that could be filled. */ #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT … #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK … /* Fields in TEGRA20_SPDIF_DATA_OUT */ /* * This register has 5 different formats: * 16-bit (BIT_MODE=00, PACK=0) * 20-bit (BIT_MODE=01, PACK=0) * 24-bit (BIT_MODE=10, PACK=0) * raw (BIT_MODE=11, PACK=0) * 16-bit packed (BIT_MODE=00, PACK=1) */ #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK … #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT … #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK … /* Fields in TEGRA20_SPDIF_DATA_IN */ /* * This register has 5 different formats: * 16-bit (BIT_MODE=00, PACK=0) * 20-bit (BIT_MODE=01, PACK=0) * 24-bit (BIT_MODE=10, PACK=0) * raw (BIT_MODE=11, PACK=0) * 16-bit packed (BIT_MODE=00, PACK=1) * * Bits 31:24 are common to all modes except 16-bit packed */ #define TEGRA20_SPDIF_DATA_IN_DATA_P … #define TEGRA20_SPDIF_DATA_IN_DATA_C … #define TEGRA20_SPDIF_DATA_IN_DATA_U … #define TEGRA20_SPDIF_DATA_IN_DATA_V … #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK … #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT … #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK … /* Fields in TEGRA20_SPDIF_CH_STA_RX_A */ /* Fields in TEGRA20_SPDIF_CH_STA_RX_B */ /* Fields in TEGRA20_SPDIF_CH_STA_RX_C */ /* Fields in TEGRA20_SPDIF_CH_STA_RX_D */ /* Fields in TEGRA20_SPDIF_CH_STA_RX_E */ /* Fields in TEGRA20_SPDIF_CH_STA_RX_F */ /* * The 6-word receive channel data page buffer holds a block (192 frames) of * channel status information. The order of receive is from LSB to MSB * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A. */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */ /* Fields in TEGRA20_SPDIF_CH_STA_TX_F */ /* * The 6-word transmit channel data page buffer holds a block (192 frames) of * channel status information. The order of transmission is from LSB to MSB * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A. */ /* Fields in TEGRA20_SPDIF_USR_STA_RX_A */ /* * This 4-word deep FIFO receives user FIFO field information. The order of * receive is from LSB to MSB bit. */ /* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */ /* * This 4-word deep FIFO transmits user FIFO field information. The order of * transmission is from LSB to MSB bit. */ struct tegra20_spdif { … }; #endif
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