/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra20_i2s.h - Definitions for Tegra20 I2S driver * * Author: Stephen Warren <[email protected]> * Copyright (C) 2010,2012 - NVIDIA, Inc. * * Based on code copyright/by: * * Copyright (c) 2009-2010, NVIDIA Corporation. * Scott Peterson <[email protected]> * * Copyright (C) 2010 Google, Inc. * Iliyan Malchev <[email protected]> */ #ifndef __TEGRA20_I2S_H__ #define __TEGRA20_I2S_H__ #include "tegra_pcm.h" /* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */ #define TEGRA20_I2S_CTRL … #define TEGRA20_I2S_STATUS … #define TEGRA20_I2S_TIMING … #define TEGRA20_I2S_FIFO_SCR … #define TEGRA20_I2S_PCM_CTRL … #define TEGRA20_I2S_NW_CTRL … #define TEGRA20_I2S_TDM_CTRL … #define TEGRA20_I2S_TDM_TX_RX_CTRL … #define TEGRA20_I2S_FIFO1 … #define TEGRA20_I2S_FIFO2 … /* Fields in TEGRA20_I2S_CTRL */ #define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE … #define TEGRA20_I2S_CTRL_FIFO1_ENABLE … #define TEGRA20_I2S_CTRL_FIFO2_ENABLE … #define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE … #define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE … #define TEGRA20_I2S_CTRL_MASTER_ENABLE … #define TEGRA20_I2S_LRCK_LEFT_LOW … #define TEGRA20_I2S_LRCK_RIGHT_LOW … #define TEGRA20_I2S_CTRL_LRCK_SHIFT … #define TEGRA20_I2S_CTRL_LRCK_MASK … #define TEGRA20_I2S_CTRL_LRCK_L_LOW … #define TEGRA20_I2S_CTRL_LRCK_R_LOW … #define TEGRA20_I2S_BIT_FORMAT_I2S … #define TEGRA20_I2S_BIT_FORMAT_RJM … #define TEGRA20_I2S_BIT_FORMAT_LJM … #define TEGRA20_I2S_BIT_FORMAT_DSP … #define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT … #define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK … #define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S … #define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM … #define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM … #define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP … #define TEGRA20_I2S_BIT_SIZE_16 … #define TEGRA20_I2S_BIT_SIZE_20 … #define TEGRA20_I2S_BIT_SIZE_24 … #define TEGRA20_I2S_BIT_SIZE_32 … #define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT … #define TEGRA20_I2S_CTRL_BIT_SIZE_MASK … #define TEGRA20_I2S_CTRL_BIT_SIZE_16 … #define TEGRA20_I2S_CTRL_BIT_SIZE_20 … #define TEGRA20_I2S_CTRL_BIT_SIZE_24 … #define TEGRA20_I2S_CTRL_BIT_SIZE_32 … #define TEGRA20_I2S_FIFO_16_LSB … #define TEGRA20_I2S_FIFO_20_LSB … #define TEGRA20_I2S_FIFO_24_LSB … #define TEGRA20_I2S_FIFO_32 … #define TEGRA20_I2S_FIFO_PACKED … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 … #define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED … #define TEGRA20_I2S_CTRL_IE_FIFO1_ERR … #define TEGRA20_I2S_CTRL_IE_FIFO2_ERR … #define TEGRA20_I2S_CTRL_QE_FIFO1 … #define TEGRA20_I2S_CTRL_QE_FIFO2 … /* Fields in TEGRA20_I2S_STATUS */ #define TEGRA20_I2S_STATUS_FIFO1_RDY … #define TEGRA20_I2S_STATUS_FIFO2_RDY … #define TEGRA20_I2S_STATUS_FIFO1_BSY … #define TEGRA20_I2S_STATUS_FIFO2_BSY … #define TEGRA20_I2S_STATUS_FIFO1_ERR … #define TEGRA20_I2S_STATUS_FIFO2_ERR … #define TEGRA20_I2S_STATUS_QS_FIFO1 … #define TEGRA20_I2S_STATUS_QS_FIFO2 … /* Fields in TEGRA20_I2S_TIMING */ #define TEGRA20_I2S_TIMING_NON_SYM_ENABLE … #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT … #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US … #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK … /* Fields in TEGRA20_I2S_FIFO_SCR */ #define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT … #define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT … #define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK … #define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR … #define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR … #define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT … #define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS … #define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS … #define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS … #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS … struct tegra20_i2s { … }; #endif
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