/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra30_ahub.h - Definitions for Tegra30 AHUB driver * * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. */ #ifndef __TEGRA30_AHUB_H__ #define __TEGRA30_AHUB_H__ /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US … #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK … #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT … #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US … #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK … /* Channel count minus 1 */ #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK … /* Channel count minus 1 */ #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT … #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US … #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK … /* Channel count minus 1 */ #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK … /* Channel count minus 1 */ #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT … #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US … #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK … #define TEGRA30_AUDIOCIF_BITS_4 … #define TEGRA30_AUDIOCIF_BITS_8 … #define TEGRA30_AUDIOCIF_BITS_12 … #define TEGRA30_AUDIOCIF_BITS_16 … #define TEGRA30_AUDIOCIF_BITS_20 … #define TEGRA30_AUDIOCIF_BITS_24 … #define TEGRA30_AUDIOCIF_BITS_28 … #define TEGRA30_AUDIOCIF_BITS_32 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 … #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 … #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 … #define TEGRA30_AUDIOCIF_EXPAND_ZERO … #define TEGRA30_AUDIOCIF_EXPAND_ONE … #define TEGRA30_AUDIOCIF_EXPAND_LFSR … #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK … #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO … #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE … #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR … #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 … #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 … #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG … #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK … #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 … #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 … #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG … #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT … #define TEGRA30_AUDIOCIF_DIRECTION_TX … #define TEGRA30_AUDIOCIF_DIRECTION_RX … #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK … #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX … #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX … #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND … #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP … #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK … #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND … #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP … #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO … #define TEGRA30_AUDIOCIF_MONO_CONV_COPY … #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT … #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK … #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO … #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY … /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ /* TEGRA30_AHUB_CHANNEL_CTRL */ #define TEGRA30_AHUB_CHANNEL_CTRL … #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE … #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN … #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN … #define TEGRA30_PACK_8_4 … #define TEGRA30_PACK_16 … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 … #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 … #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 … /* TEGRA30_AHUB_CHANNEL_CLEAR */ #define TEGRA30_AHUB_CHANNEL_CLEAR … #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE … #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT … #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET … #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET … /* TEGRA30_AHUB_CHANNEL_STATUS */ #define TEGRA30_AHUB_CHANNEL_STATUS … #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE … #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT … #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT … #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US … #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK … #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT … #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US … #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK … #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG … #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG … /* TEGRA30_AHUB_CHANNEL_TXFIFO */ #define TEGRA30_AHUB_CHANNEL_TXFIFO … #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE … #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT … /* TEGRA30_AHUB_CHANNEL_RXFIFO */ #define TEGRA30_AHUB_CHANNEL_RXFIFO … #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE … #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT … /* TEGRA30_AHUB_CIF_TX_CTRL */ #define TEGRA30_AHUB_CIF_TX_CTRL … #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE … #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT … /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ /* TEGRA30_AHUB_CIF_RX_CTRL */ #define TEGRA30_AHUB_CIF_RX_CTRL … #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE … #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT … /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ #define TEGRA30_AHUB_CONFIG_LINK_CTRL … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR … #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET … /* TEGRA30_AHUB_MISC_CTRL */ #define TEGRA30_AHUB_MISC_CTRL … #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE … #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN … #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT … #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK … /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ #define TEGRA30_AHUB_APBDMA_LIVE_STATUS … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY … #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY … /* TEGRA30_AHUB_I2S_LIVE_STATUS */ #define TEGRA30_AHUB_I2S_LIVE_STATUS … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY … #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY … /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ #define TEGRA30_AHUB_DAM_LIVE_STATUS … #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE … #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT … #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED … #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL … #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY … #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY … /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ #define TEGRA30_AHUB_SPDIF_LIVE_STATUS … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY … #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY … /* TEGRA30_AHUB_I2S_INT_MASK */ #define TEGRA30_AHUB_I2S_INT_MASK … /* TEGRA30_AHUB_DAM_INT_MASK */ #define TEGRA30_AHUB_DAM_INT_MASK … /* TEGRA30_AHUB_SPDIF_INT_MASK */ #define TEGRA30_AHUB_SPDIF_INT_MASK … /* TEGRA30_AHUB_APBIF_INT_MASK */ #define TEGRA30_AHUB_APBIF_INT_MASK … /* TEGRA30_AHUB_I2S_INT_STATUS */ #define TEGRA30_AHUB_I2S_INT_STATUS … /* TEGRA30_AHUB_DAM_INT_STATUS */ #define TEGRA30_AHUB_DAM_INT_STATUS … /* TEGRA30_AHUB_SPDIF_INT_STATUS */ #define TEGRA30_AHUB_SPDIF_INT_STATUS … /* TEGRA30_AHUB_APBIF_INT_STATUS */ #define TEGRA30_AHUB_APBIF_INT_STATUS … /* TEGRA30_AHUB_I2S_INT_SOURCE */ #define TEGRA30_AHUB_I2S_INT_SOURCE … /* TEGRA30_AHUB_DAM_INT_SOURCE */ #define TEGRA30_AHUB_DAM_INT_SOURCE … /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ #define TEGRA30_AHUB_SPDIF_INT_SOURCE … /* TEGRA30_AHUB_APBIF_INT_SOURCE */ #define TEGRA30_AHUB_APBIF_INT_SOURCE … /* TEGRA30_AHUB_I2S_INT_SET */ #define TEGRA30_AHUB_I2S_INT_SET … /* TEGRA30_AHUB_DAM_INT_SET */ #define TEGRA30_AHUB_DAM_INT_SET … /* TEGRA30_AHUB_SPDIF_INT_SET */ #define TEGRA30_AHUB_SPDIF_INT_SET … /* TEGRA30_AHUB_APBIF_INT_SET */ #define TEGRA30_AHUB_APBIF_INT_SET … /* Registers within TEGRA30_AHUB_BASE */ #define TEGRA30_AHUB_AUDIO_RX … #define TEGRA30_AHUB_AUDIO_RX_STRIDE … #define TEGRA30_AHUB_AUDIO_RX_COUNT … /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ /* * Terminology: * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, * I2S controllers, SPDIF controllers, and DAMs. * XBAR: The core cross-bar component of the AHUB. * CIF: Client Interface; the HW module connecting an audio device to the * XBAR. * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, * possibly including sample-rate conversion. * * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio * transmitted by a particular TX CIF. * * This driver is currently very simplistic; many HW features are not * exposed; DAMs are not supported, only 16-bit stereo audio is supported, * etc. */ enum tegra30_ahub_txcif { … }; enum tegra30_ahub_rxcif { … }; extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, char *dmachan, int dmachan_len, dma_addr_t *fiforeg); extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, char *dmachan, int dmachan_len, dma_addr_t *fiforeg); extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); struct tegra30_ahub_cif_conf { … }; void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, struct tegra30_ahub_cif_conf *conf); void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, struct tegra30_ahub_cif_conf *conf); struct tegra30_ahub_soc_data { … }; struct tegra30_ahub { … }; #endif
Codebase Browser
linux