linux/sound/soc/tegra/tegra30_ahub.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * tegra30_ahub.c - Tegra30 AHUB driver
 *
 * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include "tegra30_ahub.h"

#define DRV_NAME

static struct tegra30_ahub *ahub;

static inline void tegra30_apbif_write(u32 reg, u32 val)
{}

static inline u32 tegra30_apbif_read(u32 reg)
{}

static inline void tegra30_audio_write(u32 reg, u32 val)
{}

static __maybe_unused int tegra30_ahub_runtime_suspend(struct device *dev)
{}

/*
 * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data
 * is read from or sent to memory. However, that's not something the rest of
 * the driver supports right now, so we'll just treat the two clocks as one
 * for now.
 *
 * These functions should not be a plain ref-count. Instead, each active stream
 * contributes some requirement to the minimum clock rate, so starting or
 * stopping streams should dynamically adjust the clock as required.  However,
 * this is not yet implemented.
 */
static __maybe_unused int tegra30_ahub_runtime_resume(struct device *dev)
{}

int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
				  char *dmachan, int dmachan_len,
				  dma_addr_t *fiforeg)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
				  char *dmachan, int dmachan_len,
				  dma_addr_t *fiforeg)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
				   enum tegra30_ahub_txcif txcif)
{}
EXPORT_SYMBOL_GPL();

int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
{}
EXPORT_SYMBOL_GPL();

static const struct reset_control_bulk_data tegra30_ahub_resets_data[] =;

#define LAST_REG(name)

#define REG_IN_ARRAY(reg, name)

static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)
{}

static bool tegra30_ahub_apbif_volatile_reg(struct device *dev,
					    unsigned int reg)
{}

static bool tegra30_ahub_apbif_precious_reg(struct device *dev,
					    unsigned int reg)
{}

static const struct regmap_config tegra30_ahub_apbif_regmap_config =;

static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)
{}

static const struct regmap_config tegra30_ahub_ahub_regmap_config =;

static struct tegra30_ahub_soc_data soc_data_tegra30 =;

static struct tegra30_ahub_soc_data soc_data_tegra114 =;

static struct tegra30_ahub_soc_data soc_data_tegra124 =;

static const struct of_device_id tegra30_ahub_of_match[] =;

static int tegra30_ahub_probe(struct platform_device *pdev)
{}

static void tegra30_ahub_remove(struct platform_device *pdev)
{}

static const struct dev_pm_ops tegra30_ahub_pm_ops =;

static struct platform_driver tegra30_ahub_driver =;
module_platform_driver();

void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,
			  struct tegra30_ahub_cif_conf *conf)
{}
EXPORT_SYMBOL_GPL();

void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
			   struct tegra30_ahub_cif_conf *conf)
{}
EXPORT_SYMBOL_GPL();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_ALIAS();
MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);