/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra30_i2s.h - Definitions for Tegra30 I2S driver * * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. */ #ifndef __TEGRA30_I2S_H__ #define __TEGRA30_I2S_H__ #include "tegra_pcm.h" /* Register offsets from TEGRA30_I2S*_BASE */ #define TEGRA30_I2S_CTRL … #define TEGRA30_I2S_TIMING … #define TEGRA30_I2S_OFFSET … #define TEGRA30_I2S_CH_CTRL … #define TEGRA30_I2S_SLOT_CTRL … #define TEGRA30_I2S_CIF_RX_CTRL … #define TEGRA30_I2S_CIF_TX_CTRL … #define TEGRA30_I2S_FLOWCTL … #define TEGRA30_I2S_TX_STEP … #define TEGRA30_I2S_FLOW_STATUS … #define TEGRA30_I2S_FLOW_TOTAL … #define TEGRA30_I2S_FLOW_OVER … #define TEGRA30_I2S_FLOW_UNDER … #define TEGRA30_I2S_LCOEF_1_4_0 … #define TEGRA30_I2S_LCOEF_1_4_1 … #define TEGRA30_I2S_LCOEF_1_4_2 … #define TEGRA30_I2S_LCOEF_1_4_3 … #define TEGRA30_I2S_LCOEF_1_4_4 … #define TEGRA30_I2S_LCOEF_1_4_5 … #define TEGRA30_I2S_LCOEF_2_4_0 … #define TEGRA30_I2S_LCOEF_2_4_1 … #define TEGRA30_I2S_LCOEF_2_4_2 … /* Fields in TEGRA30_I2S_CTRL */ #define TEGRA30_I2S_CTRL_XFER_EN_TX … #define TEGRA30_I2S_CTRL_XFER_EN_RX … #define TEGRA30_I2S_CTRL_CG_EN … #define TEGRA30_I2S_CTRL_SOFT_RESET … #define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN … #define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT … #define TEGRA30_I2S_CTRL_OBS_SEL_MASK … #define TEGRA30_I2S_FRAME_FORMAT_LRCK … #define TEGRA30_I2S_FRAME_FORMAT_FSYNC … #define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT … #define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK … #define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK … #define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC … #define TEGRA30_I2S_CTRL_MASTER_ENABLE … #define TEGRA30_I2S_LRCK_LEFT_LOW … #define TEGRA30_I2S_LRCK_RIGHT_LOW … #define TEGRA30_I2S_CTRL_LRCK_SHIFT … #define TEGRA30_I2S_CTRL_LRCK_MASK … #define TEGRA30_I2S_CTRL_LRCK_L_LOW … #define TEGRA30_I2S_CTRL_LRCK_R_LOW … #define TEGRA30_I2S_CTRL_LPBK_ENABLE … #define TEGRA30_I2S_BIT_CODE_LINEAR … #define TEGRA30_I2S_BIT_CODE_ULAW … #define TEGRA30_I2S_BIT_CODE_ALAW … #define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT … #define TEGRA30_I2S_CTRL_BIT_CODE_MASK … #define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR … #define TEGRA30_I2S_CTRL_BIT_CODE_ULAW … #define TEGRA30_I2S_CTRL_BIT_CODE_ALAW … #define TEGRA30_I2S_BITS_8 … #define TEGRA30_I2S_BITS_12 … #define TEGRA30_I2S_BITS_16 … #define TEGRA30_I2S_BITS_20 … #define TEGRA30_I2S_BITS_24 … #define TEGRA30_I2S_BITS_28 … #define TEGRA30_I2S_BITS_32 … /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ #define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT … #define TEGRA30_I2S_CTRL_BIT_SIZE_MASK … #define TEGRA30_I2S_CTRL_BIT_SIZE_8 … #define TEGRA30_I2S_CTRL_BIT_SIZE_12 … #define TEGRA30_I2S_CTRL_BIT_SIZE_16 … #define TEGRA30_I2S_CTRL_BIT_SIZE_20 … #define TEGRA30_I2S_CTRL_BIT_SIZE_24 … #define TEGRA30_I2S_CTRL_BIT_SIZE_28 … #define TEGRA30_I2S_CTRL_BIT_SIZE_32 … /* Fields in TEGRA30_I2S_TIMING */ #define TEGRA30_I2S_TIMING_NON_SYM_ENABLE … #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT … #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US … #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK … /* Fields in TEGRA30_I2S_OFFSET */ #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT … #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US … #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK … #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT … #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US … #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK … /* Fields in TEGRA30_I2S_CH_CTRL */ /* (FSYNC width - 1) in bit clocks */ #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT … #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US … #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK … #define TEGRA30_I2S_HIGHZ_NO … #define TEGRA30_I2S_HIGHZ_YES … #define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK … #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT … #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK … #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO … #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES … #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK … #define TEGRA30_I2S_MSB_FIRST … #define TEGRA30_I2S_LSB_FIRST … #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT … #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK … #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST … #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST … #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT … #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK … #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST … #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST … #define TEGRA30_I2S_POS_EDGE … #define TEGRA30_I2S_NEG_EDGE … #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT … #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK … #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE … #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE … /* Sample size is # bits from BIT_SIZE minus this field */ #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT … #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US … #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK … #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT … #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US … #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK … /* Fields in TEGRA30_I2S_SLOT_CTRL */ /* Number of slots in frame, minus 1 */ #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT … #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US … #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK … /* TDM mode slot enable bitmask */ #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT … #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK … #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT … #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK … /* Fields in TEGRA30_I2S_CIF_RX_CTRL */ /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ /* Fields in TEGRA30_I2S_CIF_TX_CTRL */ /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ /* Fields in TEGRA30_I2S_FLOWCTL */ #define TEGRA30_I2S_FILTER_LINEAR … #define TEGRA30_I2S_FILTER_QUAD … #define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT … #define TEGRA30_I2S_FLOWCTL_FILTER_MASK … #define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR … #define TEGRA30_I2S_FLOWCTL_FILTER_QUAD … /* Fields in TEGRA30_I2S_TX_STEP */ #define TEGRA30_I2S_TX_STEP_SHIFT … #define TEGRA30_I2S_TX_STEP_MASK_US … #define TEGRA30_I2S_TX_STEP_MASK … /* Fields in TEGRA30_I2S_FLOW_STATUS */ #define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW … #define TEGRA30_I2S_FLOW_STATUS_OVERFLOW … #define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN … #define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR … #define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR … #define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN … #define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN … /* * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER, * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register. */ /* Fields in TEGRA30_I2S_LCOEF_* */ #define TEGRA30_I2S_LCOEF_COEF_SHIFT … #define TEGRA30_I2S_LCOEF_COEF_MASK_US … #define TEGRA30_I2S_LCOEF_COEF_MASK … struct tegra30_i2s_soc_data { … }; struct tegra30_i2s { … }; #endif
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