/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra210_i2s.h - Definitions for Tegra210 I2S driver * * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. * */ #ifndef __TEGRA210_I2S_H__ #define __TEGRA210_I2S_H__ /* Register offsets from I2S*_BASE */ #define TEGRA210_I2S_RX_ENABLE … #define TEGRA210_I2S_RX_SOFT_RESET … #define TEGRA210_I2S_RX_STATUS … #define TEGRA210_I2S_RX_INT_STATUS … #define TEGRA210_I2S_RX_INT_MASK … #define TEGRA210_I2S_RX_INT_SET … #define TEGRA210_I2S_RX_INT_CLEAR … #define TEGRA210_I2S_RX_CIF_CTRL … #define TEGRA210_I2S_RX_CTRL … #define TEGRA210_I2S_RX_SLOT_CTRL … #define TEGRA210_I2S_RX_CLK_TRIM … #define TEGRA210_I2S_RX_CYA … #define TEGRA210_I2S_RX_CIF_FIFO_STATUS … #define TEGRA210_I2S_TX_ENABLE … #define TEGRA210_I2S_TX_SOFT_RESET … #define TEGRA210_I2S_TX_STATUS … #define TEGRA210_I2S_TX_INT_STATUS … #define TEGRA210_I2S_TX_INT_MASK … #define TEGRA210_I2S_TX_INT_SET … #define TEGRA210_I2S_TX_INT_CLEAR … #define TEGRA210_I2S_TX_CIF_CTRL … #define TEGRA210_I2S_TX_CTRL … #define TEGRA210_I2S_TX_SLOT_CTRL … #define TEGRA210_I2S_TX_CLK_TRIM … #define TEGRA210_I2S_TX_CYA … #define TEGRA210_I2S_TX_CIF_FIFO_STATUS … #define TEGRA210_I2S_ENABLE … #define TEGRA210_I2S_SOFT_RESET … #define TEGRA210_I2S_CG … #define TEGRA210_I2S_STATUS … #define TEGRA210_I2S_INT_STATUS … #define TEGRA210_I2S_CTRL … #define TEGRA210_I2S_TIMING … #define TEGRA210_I2S_SLOT_CTRL … #define TEGRA210_I2S_CLK_TRIM … #define TEGRA210_I2S_CYA … /* Bit fields, shifts and masks */ #define I2S_DATA_SHIFT … #define I2S_CTRL_DATA_OFFSET_MASK … #define I2S_EN_SHIFT … #define I2S_EN_MASK … #define I2S_EN … #define I2S_FSYNC_WIDTH_SHIFT … #define I2S_CTRL_FSYNC_WIDTH_MASK … #define I2S_POS_EDGE … #define I2S_NEG_EDGE … #define I2S_EDGE_SHIFT … #define I2S_CTRL_EDGE_CTRL_MASK … #define I2S_CTRL_EDGE_CTRL_POS_EDGE … #define I2S_CTRL_EDGE_CTRL_NEG_EDGE … #define I2S_FMT_LRCK … #define I2S_FMT_FSYNC … #define I2S_FMT_SHIFT … #define I2S_CTRL_FRAME_FMT_MASK … #define I2S_CTRL_FRAME_FMT_LRCK_MODE … #define I2S_CTRL_FRAME_FMT_FSYNC_MODE … #define I2S_CTRL_MASTER_EN_SHIFT … #define I2S_CTRL_MASTER_EN_MASK … #define I2S_CTRL_MASTER_EN … #define I2S_CTRL_LRCK_POL_SHIFT … #define I2S_CTRL_LRCK_POL_MASK … #define I2S_CTRL_LRCK_POL_LOW … #define I2S_CTRL_LRCK_POL_HIGH … #define I2S_CTRL_LPBK_SHIFT … #define I2S_CTRL_LPBK_MASK … #define I2S_CTRL_LPBK_EN … #define I2S_BITS_8 … #define I2S_BITS_16 … #define I2S_BITS_32 … #define I2S_CTRL_BIT_SIZE_MASK … #define I2S_TIMING_CH_BIT_CNT_MASK … #define I2S_TIMING_CH_BIT_CNT_SHIFT … #define I2S_SOFT_RESET_SHIFT … #define I2S_SOFT_RESET_MASK … #define I2S_SOFT_RESET_EN … #define I2S_RX_FIFO_DEPTH … #define DEFAULT_I2S_RX_FIFO_THRESHOLD … #define DEFAULT_I2S_SLOT_MASK … enum tegra210_i2s_path { … }; struct tegra210_i2s { … }; #endif
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