/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra210_mvc.h - Definitions for Tegra210 MVC driver * * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. * */ #ifndef __TEGRA210_MVC_H__ #define __TEGRA210_MVC_H__ /* * MVC_RX registers are with respect to XBAR. * The data comes from XBAR to MVC. */ #define TEGRA210_MVC_RX_STATUS … #define TEGRA210_MVC_RX_INT_STATUS … #define TEGRA210_MVC_RX_INT_MASK … #define TEGRA210_MVC_RX_INT_SET … #define TEGRA210_MVC_RX_INT_CLEAR … #define TEGRA210_MVC_RX_CIF_CTRL … /* * MVC_TX registers are with respect to XBAR. * The data goes out of MVC. */ #define TEGRA210_MVC_TX_STATUS … #define TEGRA210_MVC_TX_INT_STATUS … #define TEGRA210_MVC_TX_INT_MASK … #define TEGRA210_MVC_TX_INT_SET … #define TEGRA210_MVC_TX_INT_CLEAR … #define TEGRA210_MVC_TX_CIF_CTRL … /* Register offsets from TEGRA210_MVC*_BASE */ #define TEGRA210_MVC_ENABLE … #define TEGRA210_MVC_SOFT_RESET … #define TEGRA210_MVC_CG … #define TEGRA210_MVC_STATUS … #define TEGRA210_MVC_INT_STATUS … #define TEGRA210_MVC_CTRL … #define TEGRA210_MVC_SWITCH … #define TEGRA210_MVC_INIT_VOL … #define TEGRA210_MVC_TARGET_VOL … #define TEGRA210_MVC_DURATION … #define TEGRA210_MVC_DURATION_INV … #define TEGRA210_MVC_POLY_N1 … #define TEGRA210_MVC_POLY_N2 … #define TEGRA210_MVC_PEAK_CTRL … #define TEGRA210_MVC_CFG_RAM_CTRL … #define TEGRA210_MVC_CFG_RAM_DATA … #define TEGRA210_MVC_PEAK_VALUE … #define TEGRA210_MVC_CONFIG_ERR_TYPE … /* Fields in TEGRA210_MVC_ENABLE */ #define TEGRA210_MVC_EN_SHIFT … #define TEGRA210_MVC_EN … #define TEGRA210_MVC_MUTE_SHIFT … #define TEGRA210_MUTE_MASK_EN … #define TEGRA210_MVC_MUTE_MASK … #define TEGRA210_MVC_MUTE_EN … #define TEGRA210_MVC_CH0_MUTE_EN … #define TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT … #define TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK … #define TEGRA210_MVC_PER_CHAN_CTRL_EN … #define TEGRA210_MVC_CURVE_TYPE_SHIFT … #define TEGRA210_MVC_CURVE_TYPE_MASK … #define TEGRA210_MVC_VOLUME_SWITCH_SHIFT … #define TEGRA210_MVC_VOLUME_SWITCH_MASK … #define TEGRA210_MVC_VOLUME_SWITCH_TRIGGER … #define TEGRA210_MVC_CTRL_DEFAULT … #define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY … #define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR … /* Fields in TEGRA210_MVC ram ctrl */ #define TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT … #define TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE … #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT … #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN … #define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT … #define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN … #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT … #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_MASK … #define REG_SIZE … #define TEGRA210_MVC_MAX_CHAN_COUNT … #define TEGRA210_MVC_REG_OFFSET(reg, i) … #define TEGRA210_MVC_GET_CHAN(reg, base) … #define TEGRA210_GET_MUTE_VAL(val) … #define NUM_GAIN_POLY_COEFFS … enum { … }; struct tegra210_mvc_gain_params { … }; struct tegra210_mvc { … }; #endif
Codebase Browser
linux