// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> * * Common Clock Framework support for all S3C64xx SoCs. */ #include <linux/slab.h> #include <linux/clk-provider.h> #include <linux/clk/samsung.h> #include <linux/of.h> #include <linux/of_address.h> #include <dt-bindings/clock/samsung,s3c64xx-clock.h> #include "clk.h" #include "clk-pll.h" /* S3C64xx clock controller register offsets. */ #define APLL_LOCK … #define MPLL_LOCK … #define EPLL_LOCK … #define APLL_CON … #define MPLL_CON … #define EPLL_CON0 … #define EPLL_CON1 … #define CLK_SRC … #define CLK_DIV0 … #define CLK_DIV1 … #define CLK_DIV2 … #define HCLK_GATE … #define PCLK_GATE … #define SCLK_GATE … #define MEM0_GATE … #define CLK_SRC2 … #define OTHERS … /* Helper macros to define clock arrays. */ #define FIXED_RATE_CLOCKS(name) … #define MUX_CLOCKS(name) … #define DIV_CLOCKS(name) … #define GATE_CLOCKS(name) … /* Helper macros for gate types present on S3C64xx. */ #define GATE_BUS(_id, cname, pname, o, b) … #define GATE_SCLK(_id, cname, pname, o, b) … #define GATE_ON(_id, cname, pname, o, b) … static void __iomem *reg_base; static bool is_s3c6400; /* * List of controller registers to be saved and restored during * a suspend/resume cycle. */ static unsigned long s3c64xx_clk_regs[] __initdata = …; static unsigned long s3c6410_clk_regs[] __initdata = …; /* List of parent clocks common for all S3C64xx SoCs. */ PNAME(spi_mmc_p) = …; PNAME(uart_p) = …; PNAME(audio0_p) = …; PNAME(audio1_p) = …; PNAME(mfc_p) = …; PNAME(apll_p) = …; PNAME(mpll_p) = …; PNAME(epll_p) = …; PNAME(hclkx2_p) = …; /* S3C6400-specific parent clocks. */ PNAME(scaler_lcd_p6400) = …; PNAME(irda_p6400) = …; PNAME(uhost_p6400) = …; /* S3C6410-specific parent clocks. */ PNAME(clk27_p6410) = …; PNAME(scaler_lcd_p6410) = …; PNAME(irda_p6410) = …; PNAME(uhost_p6410) = …; PNAME(audio2_p6410) = …; /* Fixed rate clocks generated outside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = …; /* Fixed rate clocks generated inside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = …; /* List of clock muxes present on all S3C64xx SoCs. */ MUX_CLOCKS(s3c64xx_mux_clks) __initdata = …; /* List of clock muxes present on S3C6400. */ MUX_CLOCKS(s3c6400_mux_clks) __initdata = …; /* List of clock muxes present on S3C6410. */ MUX_CLOCKS(s3c6410_mux_clks) __initdata = …; /* List of clock dividers present on all S3C64xx SoCs. */ DIV_CLOCKS(s3c64xx_div_clks) __initdata = …; /* List of clock dividers present on S3C6400. */ DIV_CLOCKS(s3c6400_div_clks) __initdata = …; /* List of clock dividers present on S3C6410. */ DIV_CLOCKS(s3c6410_div_clks) __initdata = …; /* List of clock gates present on all S3C64xx SoCs. */ GATE_CLOCKS(s3c64xx_gate_clks) __initdata = …; /* List of clock gates present on S3C6400. */ GATE_CLOCKS(s3c6400_gate_clks) __initdata = …; /* List of clock gates present on S3C6410. */ GATE_CLOCKS(s3c6410_gate_clks) __initdata = …; /* List of PLL clocks. */ static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = …; /* Aliases for common s3c64xx clocks. */ static struct samsung_clock_alias s3c64xx_clock_aliases[] = …; /* Aliases for s3c6400-specific clocks. */ static struct samsung_clock_alias s3c6400_clock_aliases[] = …; /* Aliases for s3c6410-specific clocks. */ static struct samsung_clock_alias s3c6410_clock_aliases[] = …; static void __init s3c64xx_clk_register_fixed_ext( struct samsung_clk_provider *ctx, unsigned long fin_pll_f, unsigned long xusbxti_f) { … } /* Register s3c64xx clocks. */ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, unsigned long xusbxti_f, bool s3c6400, void __iomem *base) { … } static void __init s3c6400_clk_init(struct device_node *np) { … } CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init); static void __init s3c6410_clk_init(struct device_node *np) { … } CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
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