/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra210_sfc.h - Definitions for Tegra210 SFC driver * * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. * */ #ifndef __TEGRA210_SFC_H__ #define __TEGRA210_SFC_H__ /* * SFC_RX registers are with respect to XBAR. * The data comes from XBAR to SFC. */ #define TEGRA210_SFC_RX_STATUS … #define TEGRA210_SFC_RX_INT_STATUS … #define TEGRA210_SFC_RX_INT_MASK … #define TEGRA210_SFC_RX_INT_SET … #define TEGRA210_SFC_RX_INT_CLEAR … #define TEGRA210_SFC_RX_CIF_CTRL … #define TEGRA210_SFC_RX_FREQ … /* * SFC_TX registers are with respect to XBAR. * The data goes out of SFC. */ #define TEGRA210_SFC_TX_STATUS … #define TEGRA210_SFC_TX_INT_STATUS … #define TEGRA210_SFC_TX_INT_MASK … #define TEGRA210_SFC_TX_INT_SET … #define TEGRA210_SFC_TX_INT_CLEAR … #define TEGRA210_SFC_TX_CIF_CTRL … #define TEGRA210_SFC_TX_FREQ … /* Register offsets from TEGRA210_SFC*_BASE */ #define TEGRA210_SFC_ENABLE … #define TEGRA210_SFC_SOFT_RESET … #define TEGRA210_SFC_CG … #define TEGRA210_SFC_STATUS … #define TEGRA210_SFC_INT_STATUS … #define TEGRA210_SFC_COEF_RAM … #define TEGRA210_SFC_CFG_RAM_CTRL … #define TEGRA210_SFC_CFG_RAM_DATA … /* Fields in TEGRA210_SFC_ENABLE */ #define TEGRA210_SFC_EN_SHIFT … #define TEGRA210_SFC_EN … #define TEGRA210_SFC_NUM_RATES … /* Fields in TEGRA210_SFC_COEF_RAM */ #define TEGRA210_SFC_COEF_RAM_EN … #define TEGRA210_SFC_SOFT_RESET_EN … /* Coefficients */ #define TEGRA210_SFC_COEF_RAM_DEPTH … #define TEGRA210_SFC_RAM_CTRL_RW_WRITE … #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN … #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN … enum tegra210_sfc_path { … }; struct tegra210_sfc { … }; #endif
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