linux/sound/soc/tegra/tegra210_mixer.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * tegra210_mixer.h - Definitions for Tegra210 MIXER driver
 *
 * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
 *
 */

#ifndef __TEGRA210_MIXER_H__
#define __TEGRA210_MIXER_H__

/* XBAR_RX related MIXER offsets */
#define TEGRA210_MIXER_RX1_SOFT_RESET …
#define TEGRA210_MIXER_RX1_STATUS …
#define TEGRA210_MIXER_RX1_CIF_CTRL …
#define TEGRA210_MIXER_RX1_CTRL …
#define TEGRA210_MIXER_RX1_PEAK_CTRL …
#define TEGRA210_MIXER_RX1_SAMPLE_COUNT …

/* XBAR_TX related MIXER offsets */
#define TEGRA210_MIXER_TX1_ENABLE …
#define TEGRA210_MIXER_TX1_SOFT_RESET …
#define TEGRA210_MIXER_TX1_STATUS …
#define TEGRA210_MIXER_TX1_INT_STATUS …
#define TEGRA210_MIXER_TX1_INT_MASK …
#define TEGRA210_MIXER_TX1_INT_SET …
#define TEGRA210_MIXER_TX1_INT_CLEAR …
#define TEGRA210_MIXER_TX1_CIF_CTRL …
#define TEGRA210_MIXER_TX1_ADDER_CONFIG …

/* MIXER related offsets */
#define TEGRA210_MIXER_ENABLE …
#define TEGRA210_MIXER_SOFT_RESET …
#define TEGRA210_MIXER_CG …
#define TEGRA210_MIXER_STATUS …
#define TEGRA210_MIXER_INT_STATUS …
#define TEGRA210_MIXER_GAIN_CFG_RAM_CTRL …
#define TEGRA210_MIXER_GAIN_CFG_RAM_DATA …
#define TEGRA210_MIXER_PEAKM_RAM_CTRL …
#define TEGRA210_MIXER_PEAKM_RAM_DATA …
#define TEGRA210_MIXER_CTRL …

#define TEGRA210_MIXER_TX2_ADDER_CONFIG …
#define TEGRA210_MIXER_TX3_ADDER_CONFIG …
#define TEGRA210_MIXER_TX4_ADDER_CONFIG …
#define TEGRA210_MIXER_TX5_ADDER_CONFIG …

#define TEGRA210_MIXER_TX2_ENABLE …
#define TEGRA210_MIXER_TX3_ENABLE …
#define TEGRA210_MIXER_TX4_ENABLE …
#define TEGRA210_MIXER_TX5_ENABLE …

/* Fields in TEGRA210_MIXER_ENABLE */
#define TEGRA210_MIXER_ENABLE_SHIFT …
#define TEGRA210_MIXER_ENABLE_MASK …
#define TEGRA210_MIXER_EN …

/* Fields in TEGRA210_MIXER_GAIN_CFG_RAM_CTRL */
#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0 …
#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE …

#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT …
#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_MASK …
#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE …

#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT …
#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_MASK …
#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN …

#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT …
#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_MASK …
#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN …

#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT …
#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK …

#define TEGRA210_MIXER_REG_STRIDE …
#define TEGRA210_MIXER_RX_MAX …
#define TEGRA210_MIXER_RX_LIMIT …
#define TEGRA210_MIXER_TX_MAX …
#define TEGRA210_MIXER_TX_LIMIT …

#define REG_CFG_DONE_TRIGGER …
#define VAL_CFG_DONE_TRIGGER …

#define NUM_GAIN_POLY_COEFFS …
#define NUM_DURATION_PARMS …

struct tegra210_mixer_gain_params { … };

struct tegra210_mixer { … };

#endif