/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra210_mbdrc.h - Definitions for Tegra210 MBDRC driver * * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * */ #ifndef __TEGRA210_MBDRC_H__ #define __TEGRA210_MBDRC_H__ #include <linux/platform_device.h> #include <sound/soc.h> /* Register offsets from TEGRA210_MBDRC*_BASE */ #define TEGRA210_MBDRC_SOFT_RESET … #define TEGRA210_MBDRC_CG … #define TEGRA210_MBDRC_STATUS … #define TEGRA210_MBDRC_CFG … #define TEGRA210_MBDRC_CHANNEL_MASK … #define TEGRA210_MBDRC_MASTER_VOL … #define TEGRA210_MBDRC_FAST_FACTOR … #define TEGRA210_MBDRC_FILTER_COUNT … #define TEGRA210_MBDRC_FILTER_PARAM_STRIDE … #define TEGRA210_MBDRC_IIR_CFG … #define TEGRA210_MBDRC_IN_ATTACK … #define TEGRA210_MBDRC_IN_RELEASE … #define TEGRA210_MBDRC_FAST_ATTACK … #define TEGRA210_MBDRC_IN_THRESHOLD … #define TEGRA210_MBDRC_OUT_THRESHOLD … #define TEGRA210_MBDRC_RATIO_1ST … #define TEGRA210_MBDRC_RATIO_2ND … #define TEGRA210_MBDRC_RATIO_3RD … #define TEGRA210_MBDRC_RATIO_4TH … #define TEGRA210_MBDRC_RATIO_5TH … #define TEGRA210_MBDRC_MAKEUP_GAIN … #define TEGRA210_MBDRC_INIT_GAIN … #define TEGRA210_MBDRC_GAIN_ATTACK … #define TEGRA210_MBDRC_GAIN_RELEASE … #define TEGRA210_MBDRC_FAST_RELEASE … #define TEGRA210_MBDRC_CFG_RAM_CTRL … #define TEGRA210_MBDRC_CFG_RAM_DATA … #define TEGRA210_MBDRC_MAX_REG … /* Fields for TEGRA210_MBDRC_CFG */ #define TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT … #define TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK … #define TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT … #define TEGRA210_MBDRC_CFG_PEAK_RMS_MASK … #define TEGRA210_MBDRC_CFG_PEAK … #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT … #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK … #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_FLEX … #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT … #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK … #define TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT … #define TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK … #define TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT … #define TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK … #define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS … /* Fields for TEGRA210_MBDRC_CHANNEL_MASK */ #define TEGRA210_MBDRC_CHANNEL_MASK_SHIFT … #define TEGRA210_MBDRC_CHANNEL_MASK_MASK … /* Fields for TEGRA210_MBDRC_MASTER_VOL */ #define TEGRA210_MBDRC_MASTER_VOL_SHIFT … #define TEGRA210_MBDRC_MASTER_VOL_MIN … #define TEGRA210_MBDRC_MASTER_VOL_MAX … /* Fields for TEGRA210_MBDRC_FAST_FACTOR */ #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT … #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_MASK … #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT … #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK … /* Fields for TEGRA210_MBDRC_IIR_CFG */ #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT … #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK … /* Fields for TEGRA210_MBDRC_IN_ATTACK */ #define TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT … #define TEGRA210_MBDRC_IN_ATTACK_TC_MASK … /* Fields for TEGRA210_MBDRC_IN_RELEASE */ #define TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT … #define TEGRA210_MBDRC_IN_RELEASE_TC_MASK … /* Fields for TEGRA210_MBDRC_FAST_ATTACK */ #define TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT … #define TEGRA210_MBDRC_FAST_ATTACK_TC_MASK … /* Fields for TEGRA210_MBDRC_IN_THRESHOLD / TEGRA210_MBDRC_OUT_THRESHOLD */ #define TEGRA210_MBDRC_THRESH_4TH_SHIFT … #define TEGRA210_MBDRC_THRESH_4TH_MASK … #define TEGRA210_MBDRC_THRESH_3RD_SHIFT … #define TEGRA210_MBDRC_THRESH_3RD_MASK … #define TEGRA210_MBDRC_THRESH_2ND_SHIFT … #define TEGRA210_MBDRC_THRESH_2ND_MASK … #define TEGRA210_MBDRC_THRESH_1ST_SHIFT … #define TEGRA210_MBDRC_THRESH_1ST_MASK … /* Fields for TEGRA210_MBDRC_RATIO_1ST */ #define TEGRA210_MBDRC_RATIO_1ST_SHIFT … #define TEGRA210_MBDRC_RATIO_1ST_MASK … /* Fields for TEGRA210_MBDRC_RATIO_2ND */ #define TEGRA210_MBDRC_RATIO_2ND_SHIFT … #define TEGRA210_MBDRC_RATIO_2ND_MASK … /* Fields for TEGRA210_MBDRC_RATIO_3RD */ #define TEGRA210_MBDRC_RATIO_3RD_SHIFT … #define TEGRA210_MBDRC_RATIO_3RD_MASK … /* Fields for TEGRA210_MBDRC_RATIO_4TH */ #define TEGRA210_MBDRC_RATIO_4TH_SHIFT … #define TEGRA210_MBDRC_RATIO_4TH_MASK … /* Fields for TEGRA210_MBDRC_RATIO_5TH */ #define TEGRA210_MBDRC_RATIO_5TH_SHIFT … #define TEGRA210_MBDRC_RATIO_5TH_MASK … /* Fields for TEGRA210_MBDRC_MAKEUP_GAIN */ #define TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT … #define TEGRA210_MBDRC_MAKEUP_GAIN_MASK … /* Fields for TEGRA210_MBDRC_INIT_GAIN */ #define TEGRA210_MBDRC_INIT_GAIN_SHIFT … #define TEGRA210_MBDRC_INIT_GAIN_MASK … /* Fields for TEGRA210_MBDRC_GAIN_ATTACK */ #define TEGRA210_MBDRC_GAIN_ATTACK_SHIFT … #define TEGRA210_MBDRC_GAIN_ATTACK_MASK … /* Fields for TEGRA210_MBDRC_GAIN_RELEASE */ #define TEGRA210_MBDRC_GAIN_RELEASE_SHIFT … #define TEGRA210_MBDRC_GAIN_RELEASE_MASK … /* Fields for TEGRA210_MBDRC_FAST_RELEASE */ #define TEGRA210_MBDRC_FAST_RELEASE_SHIFT … #define TEGRA210_MBDRC_FAST_RELEASE_MASK … #define TEGRA210_MBDRC_RAM_CTRL_RW_READ … #define TEGRA210_MBDRC_RAM_CTRL_RW_WRITE … #define TEGRA210_MBDRC_RAM_CTRL_ADDR_INIT_EN … #define TEGRA210_MBDRC_RAM_CTRL_SEQ_ACCESS_EN … #define TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK … /* * Order and size of each structure element for following structures should not * be altered size order of elements and their size are based on PEQ co-eff ram * and shift ram layout. */ #define TEGRA210_MBDRC_THRESHOLD_NUM … #define TEGRA210_MBDRC_RATIO_NUM … #define TEGRA210_MBDRC_MAX_BIQUAD_STAGES … /* Order of these enums are same as the order of band specific hw registers */ enum { … }; struct tegra210_mbdrc_band_params { … }; struct tegra210_mbdrc_config { … }; int tegra210_mbdrc_regmap_init(struct platform_device *pdev); int tegra210_mbdrc_component_init(struct snd_soc_component *cmpnt); int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt); #endif
Codebase Browser
linux