/* SPDX-License-Identifier: GPL-2.0-only */ /* * tegra186_dspk.h - Definitions for Tegra186 DSPK driver * * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. * */ #ifndef __TEGRA186_DSPK_H__ #define __TEGRA186_DSPK_H__ /* Register offsets from DSPK BASE */ #define TEGRA186_DSPK_RX_STATUS … #define TEGRA186_DSPK_RX_INT_STATUS … #define TEGRA186_DSPK_RX_INT_MASK … #define TEGRA186_DSPK_RX_INT_SET … #define TEGRA186_DSPK_RX_INT_CLEAR … #define TEGRA186_DSPK_RX_CIF_CTRL … #define TEGRA186_DSPK_ENABLE … #define TEGRA186_DSPK_SOFT_RESET … #define TEGRA186_DSPK_CG … #define TEGRA186_DSPK_STATUS … #define TEGRA186_DSPK_INT_STATUS … #define TEGRA186_DSPK_CORE_CTRL … #define TEGRA186_DSPK_CODEC_CTRL … /* DSPK CORE CONTROL fields */ #define CH_SEL_SHIFT … #define TEGRA186_DSPK_CHANNEL_SELECT_MASK … #define DSPK_OSR_SHIFT … #define TEGRA186_DSPK_OSR_MASK … #define LRSEL_POL_SHIFT … #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK … #define TEGRA186_DSPK_RX_FIFO_DEPTH … #define DSPK_OSR_FACTOR … /* DSPK interface clock ratio */ #define DSPK_CLK_RATIO … enum tegra_dspk_osr { … }; enum tegra_dspk_ch_sel { … }; enum tegra_dspk_lrsel { … }; struct tegra186_dspk { … }; #endif
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