/* SPDX-License-Identifier: GPL-2.0-only */ /* * ALSA SoC McASP Audio Layer for TI DAVINCI processor * * MCASP related definitions * * Author: Nirmal Pandey <[email protected]>, * Suresh Rajashekara <[email protected]> * Steve Chen <[email protected]> * * Copyright: (C) 2009 MontaVista Software, Inc., <[email protected]> * Copyright: (C) 2009 Texas Instruments, India */ #ifndef DAVINCI_MCASP_H #define DAVINCI_MCASP_H /* * McASP register definitions */ #define DAVINCI_MCASP_PID_REG … #define DAVINCI_MCASP_PWREMUMGT_REG … #define DAVINCI_MCASP_PFUNC_REG … #define DAVINCI_MCASP_PDIR_REG … #define DAVINCI_MCASP_PDOUT_REG … #define DAVINCI_MCASP_PDSET_REG … #define DAVINCI_MCASP_PDCLR_REG … #define DAVINCI_MCASP_TLGC_REG … #define DAVINCI_MCASP_TLMR_REG … #define DAVINCI_MCASP_GBLCTL_REG … #define DAVINCI_MCASP_AMUTE_REG … #define DAVINCI_MCASP_LBCTL_REG … #define DAVINCI_MCASP_TXDITCTL_REG … #define DAVINCI_MCASP_GBLCTLR_REG … #define DAVINCI_MCASP_RXMASK_REG … #define DAVINCI_MCASP_RXFMT_REG … #define DAVINCI_MCASP_RXFMCTL_REG … #define DAVINCI_MCASP_ACLKRCTL_REG … #define DAVINCI_MCASP_AHCLKRCTL_REG … #define DAVINCI_MCASP_RXTDM_REG … #define DAVINCI_MCASP_EVTCTLR_REG … #define DAVINCI_MCASP_RXSTAT_REG … #define DAVINCI_MCASP_RXTDMSLOT_REG … #define DAVINCI_MCASP_RXCLKCHK_REG … #define DAVINCI_MCASP_REVTCTL_REG … #define DAVINCI_MCASP_GBLCTLX_REG … #define DAVINCI_MCASP_TXMASK_REG … #define DAVINCI_MCASP_TXFMT_REG … #define DAVINCI_MCASP_TXFMCTL_REG … #define DAVINCI_MCASP_ACLKXCTL_REG … #define DAVINCI_MCASP_AHCLKXCTL_REG … #define DAVINCI_MCASP_TXTDM_REG … #define DAVINCI_MCASP_EVTCTLX_REG … #define DAVINCI_MCASP_TXSTAT_REG … #define DAVINCI_MCASP_TXTDMSLOT_REG … #define DAVINCI_MCASP_TXCLKCHK_REG … #define DAVINCI_MCASP_XEVTCTL_REG … /* Left(even TDM Slot) Channel Status Register File */ #define DAVINCI_MCASP_DITCSRA_REG … /* Right(odd TDM slot) Channel Status Register File */ #define DAVINCI_MCASP_DITCSRB_REG … /* Left(even TDM slot) User Data Register File */ #define DAVINCI_MCASP_DITUDRA_REG … /* Right(odd TDM Slot) User Data Register File */ #define DAVINCI_MCASP_DITUDRB_REG … /* Serializer n Control Register */ #define DAVINCI_MCASP_XRSRCTL_BASE_REG … #define DAVINCI_MCASP_XRSRCTL_REG(n) … /* Transmit Buffer for Serializer n */ #define DAVINCI_MCASP_TXBUF_REG(n) … /* Receive Buffer for Serializer n */ #define DAVINCI_MCASP_RXBUF_REG(n) … /* McASP FIFO Registers */ #define DAVINCI_MCASP_V2_AFIFO_BASE … #define DAVINCI_MCASP_V3_AFIFO_BASE … /* FIFO register offsets from AFIFO base */ #define MCASP_WFIFOCTL_OFFSET … #define MCASP_WFIFOSTS_OFFSET … #define MCASP_RFIFOCTL_OFFSET … #define MCASP_RFIFOSTS_OFFSET … /* * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management * Register Bits */ #define MCASP_FREE … #define MCASP_SOFT … /* * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode */ #define PIN_BIT_AXR(n) … #define PIN_BIT_AMUTE … #define PIN_BIT_ACLKX … #define PIN_BIT_AHCLKX … #define PIN_BIT_AFSX … #define PIN_BIT_ACLKR … #define PIN_BIT_AHCLKR … #define PIN_BIT_AFSR … /* * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits */ #define DITEN … #define VA … #define VB … /* * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits */ #define TXROT(val) … #define TXSEL … #define TXSSZ(val) … #define TXPBIT(val) … #define TXPAD(val) … #define TXORD … #define FSXDLY(val) … /* * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits */ #define RXROT(val) … #define RXSEL … #define RXSSZ(val) … #define RXPBIT(val) … #define RXPAD(val) … #define RXORD … #define FSRDLY(val) … /* * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits */ #define FSXPOL … #define AFSXE … #define FSXDUR … #define FSXMOD(val) … /* * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits */ #define FSRPOL … #define AFSRE … #define FSRDUR … #define FSRMOD(val) … /* * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits */ #define ACLKXDIV(val) … #define ACLKXE … #define TX_ASYNC … #define ACLKXPOL … #define ACLKXDIV_MASK … /* * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits */ #define ACLKRDIV(val) … #define ACLKRE … #define RX_ASYNC … #define ACLKRPOL … #define ACLKRDIV_MASK … /* * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control * Register Bits */ #define AHCLKXDIV(val) … #define AHCLKXPOL … #define AHCLKXE … #define AHCLKXDIV_MASK … /* * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control * Register Bits */ #define AHCLKRDIV(val) … #define AHCLKRPOL … #define AHCLKRE … #define AHCLKRDIV_MASK … /* * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits */ #define MODE(val) … #define DISMOD_3STATE … #define DISMOD_LOW … #define DISMOD_HIGH … #define DISMOD_VAL(x) … #define DISMOD_MASK … #define TXSTATE … #define RXSTATE … #define SRMOD_MASK … #define SRMOD_INACTIVE … /* * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits */ #define LBEN … #define LBORD … #define LBGENMODE(val) … /* * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration */ #define TXTDMS(n) … /* * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration */ #define RXTDMS(n) … /* * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits */ #define RXCLKRST … #define RXHCLKRST … #define RXSERCLR … #define RXSMRST … #define RXFSRST … #define TXCLKRST … #define TXHCLKRST … #define TXSERCLR … #define TXSMRST … #define TXFSRST … /* * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits */ #define XRERR … #define XRDATA … /* * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits */ #define MUTENA(val) … #define MUTEINPOL … #define MUTEINENA … #define MUTEIN … #define MUTER … #define MUTEX … #define MUTEFSR … #define MUTEFSX … #define MUTEBADCLKR … #define MUTEBADCLKX … #define MUTERXDMAERR … #define MUTETXDMAERR … /* * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits */ #define RXDATADMADIS … /* * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits */ #define TXDATADMADIS … /* * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits */ #define ROVRN … /* * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits */ #define XUNDRN … /* * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits */ #define FIFO_ENABLE … #define NUMEVT_MASK … #define NUMEVT(x) … #define NUMDMA_MASK … /* Source of High-frequency transmit/receive clock */ #define MCASP_CLK_HCLK_AHCLK … #define MCASP_CLK_HCLK_AUXCLK … /* clock divider IDs */ #define MCASP_CLKDIV_AUXCLK … #define MCASP_CLKDIV_BCLK … #define MCASP_CLKDIV_BCLK_FS_RATIO … #endif /* DAVINCI_MCASP_H */
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