/* SPDX-License-Identifier: GPL-2.0 */ /* * OMAP Multi-Channel Buffered Serial Port * * Contact: Jarkko Nikula <[email protected]> * Peter Ujfalusi <[email protected]> */ #ifndef __OMAP_MCBSP_PRIV_H__ #define __OMAP_MCBSP_PRIV_H__ #include <linux/platform_data/asoc-ti-mcbsp.h> #ifdef CONFIG_ARCH_OMAP1 #define mcbsp_omap1 … #else #define mcbsp_omap1() … #endif /* McBSP register numbers. Register address offset = num * reg_step */ enum { … }; /************************** McBSP SPCR1 bit definitions ***********************/ #define RRST … #define RRDY … #define RFULL … #define RSYNC_ERR … #define RINTM(value) … #define ABIS … #define DXENA … #define CLKSTP(value) … #define RJUST(value) … #define ALB … #define DLB … /************************** McBSP SPCR2 bit definitions ***********************/ #define XRST … #define XRDY … #define XEMPTY … #define XSYNC_ERR … #define XINTM(value) … #define GRST … #define FRST … #define SOFT … #define FREE … /************************** McBSP PCR bit definitions *************************/ #define CLKRP … #define CLKXP … #define FSRP … #define FSXP … #define DR_STAT … #define DX_STAT … #define CLKS_STAT … #define SCLKME … #define CLKRM … #define CLKXM … #define FSRM … #define FSXM … #define RIOEN … #define XIOEN … #define IDLE_EN … /************************** McBSP RCR1 bit definitions ************************/ #define RWDLEN1(value) … #define RFRLEN1(value) … /************************** McBSP XCR1 bit definitions ************************/ #define XWDLEN1(value) … #define XFRLEN1(value) … /*************************** McBSP RCR2 bit definitions ***********************/ #define RDATDLY(value) … #define RFIG … #define RCOMPAND(value) … #define RWDLEN2(value) … #define RFRLEN2(value) … #define RPHASE … /*************************** McBSP XCR2 bit definitions ***********************/ #define XDATDLY(value) … #define XFIG … #define XCOMPAND(value) … #define XWDLEN2(value) … #define XFRLEN2(value) … #define XPHASE … /************************* McBSP SRGR1 bit definitions ************************/ #define CLKGDV(value) … #define FWID(value) … /************************* McBSP SRGR2 bit definitions ************************/ #define FPER(value) … #define FSGM … #define CLKSM … #define CLKSP … #define GSYNC … /************************* McBSP MCR1 bit definitions *************************/ #define RMCM … #define RCBLK(value) … #define RPABLK(value) … #define RPBBLK(value) … /************************* McBSP MCR2 bit definitions *************************/ #define XMCM(value) … #define XCBLK(value) … #define XPABLK(value) … #define XPBBLK(value) … /*********************** McBSP XCCR bit definitions *************************/ #define XDISABLE … #define XDMAEN … #define DILB … #define XFULL_CYCLE … #define DXENDLY(value) … #define PPCONNECT … #define EXTCLKGATE … /********************** McBSP RCCR bit definitions *************************/ #define RDISABLE … #define RDMAEN … #define RFULL_CYCLE … /********************** McBSP SYSCONFIG bit definitions ********************/ #define SOFTRST … #define ENAWAKEUP … #define SIDLEMODE(value) … #define CLOCKACTIVITY(value) … /********************** McBSP DMA operating modes **************************/ #define MCBSP_DMA_MODE_ELEMENT … #define MCBSP_DMA_MODE_THRESHOLD … /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/ #define RSYNCERREN … #define RFSREN … #define REOFEN … #define RRDYEN … #define RUNDFLEN … #define ROVFLEN … #define XSYNCERREN … #define XFSXEN … #define XEOFEN … #define XRDYEN … #define XUNDFLEN … #define XOVFLEN … #define XEMPTYEOFEN … /* Clock signal muxing options */ #define CLKR_SRC_CLKR … #define CLKR_SRC_CLKX … #define FSR_SRC_FSR … #define FSR_SRC_FSX … /* McBSP functional clock sources */ #define MCBSP_CLKS_PRCM_SRC … #define MCBSP_CLKS_PAD_SRC … /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { … }; struct omap_mcbsp_st_data; struct omap_mcbsp { … }; static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { … } static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { … } #define MCBSP_READ(mcbsp, reg) … #define MCBSP_WRITE(mcbsp, reg, val) … #define MCBSP_READ_CACHE(mcbsp, reg) … /* Sidetone specific API */ int omap_mcbsp_st_init(struct platform_device *pdev); int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp); int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp); #endif /* __OMAP_MCBSP_PRIV_H__ */
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