/* SPDX-License-Identifier: GPL-2.0 */ /* * Socionext UniPhier AIO ALSA driver. * * Copyright (c) 2016-2018 Socionext Inc. */ #ifndef SND_UNIPHIER_AIO_H__ #define SND_UNIPHIER_AIO_H__ #include <linux/spinlock.h> #include <linux/types.h> #include <sound/pcm.h> #include <sound/soc.h> #include <sound/soc-dai.h> struct platform_device; enum ID_PORT_TYPE { … }; enum ID_PORT_DIR { … }; enum IEC61937_PC { … }; /* IEC61937 Repetition period of data-burst in IEC60958 frames */ #define IEC61937_FRM_STR_AC3 … #define IEC61937_FRM_STR_MPA … #define IEC61937_FRM_STR_MP3 … #define IEC61937_FRM_STR_DTS1 … #define IEC61937_FRM_STR_DTS2 … #define IEC61937_FRM_STR_DTS3 … #define IEC61937_FRM_STR_AAC … /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */ #define IEC61937_FRM_PAU_AC3 … #define IEC61937_FRM_PAU_MPA … #define IEC61937_FRM_PAU_MP3 … #define IEC61937_FRM_PAU_DTS1 … #define IEC61937_FRM_PAU_DTS2 … #define IEC61937_FRM_PAU_DTS3 … #define IEC61937_FRM_PAU_AAC … /* IEC61937 Pa and Pb */ #define IEC61937_HEADER_SIGN … #define AUD_HW_PCMIN1 … #define AUD_HW_PCMIN2 … #define AUD_HW_PCMIN3 … #define AUD_HW_IECIN1 … #define AUD_HW_DIECIN1 … #define AUD_NAME_PCMIN1 … #define AUD_NAME_PCMIN2 … #define AUD_NAME_PCMIN3 … #define AUD_NAME_IECIN1 … #define AUD_NAME_DIECIN1 … #define AUD_HW_HPCMOUT1 … #define AUD_HW_PCMOUT1 … #define AUD_HW_PCMOUT2 … #define AUD_HW_PCMOUT3 … #define AUD_HW_EPCMOUT1 … #define AUD_HW_EPCMOUT2 … #define AUD_HW_EPCMOUT3 … #define AUD_HW_EPCMOUT6 … #define AUD_HW_HIECOUT1 … #define AUD_HW_IECOUT1 … #define AUD_HW_CMASTER … #define AUD_NAME_HPCMOUT1 … #define AUD_NAME_PCMOUT1 … #define AUD_NAME_PCMOUT2 … #define AUD_NAME_PCMOUT3 … #define AUD_NAME_EPCMOUT1 … #define AUD_NAME_EPCMOUT2 … #define AUD_NAME_EPCMOUT3 … #define AUD_NAME_EPCMOUT6 … #define AUD_NAME_HIECOUT1 … #define AUD_NAME_IECOUT1 … #define AUD_NAME_CMASTER … #define AUD_NAME_HIECCOMPOUT1 … #define AUD_NAME_IECCOMPOUT1 … #define AUD_GNAME_HDMI … #define AUD_GNAME_LINE … #define AUD_GNAME_AUX … #define AUD_GNAME_IEC … #define AUD_CLK_IO … #define AUD_CLK_A1 … #define AUD_CLK_F1 … #define AUD_CLK_A2 … #define AUD_CLK_F2 … #define AUD_CLK_A … #define AUD_CLK_F … #define AUD_CLK_APLL … #define AUD_CLK_RX0 … #define AUD_CLK_USB0 … #define AUD_CLK_HSC0 … #define AUD_PLL_A1 … #define AUD_PLL_F1 … #define AUD_PLL_A2 … #define AUD_PLL_F2 … #define AUD_PLL_APLL … #define AUD_PLL_RX0 … #define AUD_PLL_USB0 … #define AUD_PLL_HSC0 … #define AUD_PLLDIV_1_2 … #define AUD_PLLDIV_1_3 … #define AUD_PLLDIV_1_1 … #define AUD_PLLDIV_2_3 … #define AUD_VOL_INIT … #define AUD_VOL_MAX … #define AUD_VOL_FADE_TIME … #define AUD_RING_SIZE … #define AUD_MIN_FRAGMENT … #define AUD_MAX_FRAGMENT … #define AUD_MIN_FRAGMENT_SIZE … #define AUD_MAX_FRAGMENT_SIZE … /* max 5 slots, 10 channels, 2 channel in 1 slot */ #define AUD_MAX_SLOTSEL … /* * This is a selector for virtual register map of AIO. * * map: Specify the index of virtual register map. * hw : Specify the ID of real register map, selector uses this value. * A meaning of this value depends specification of SoC. */ struct uniphier_aio_selector { … }; /** * 'SoftWare MAPping' setting of UniPhier AIO registers. * * We have to setup 'virtual' register maps to access 'real' registers of AIO. * This feature is legacy and meaningless but AIO needs this to work. * * Each hardware blocks have own virtual register maps as following: * * Address Virtual Real * ------- --------- --------------- * 0x12000 DMAC map0 --> [selector] --> DMAC hardware 3 * 0x12080 DMAC map1 --> [selector] --> DMAC hardware 1 * ... * 0x42000 Port map0 --> [selector] --> Port hardware 1 * 0x42400 Port map1 --> [selector] --> Port hardware 2 * ... * * ch : Input or output channel of DMAC * rb : Ring buffer * iport: PCM input port * iif : Input interface * oport: PCM output port * oif : Output interface * och : Output channel of DMAC for sampling rate converter * * These are examples for sound data paths: * * For caputure device: * (outer of AIO) -> iport -> iif -> ch -> rb -> (CPU) * For playback device: * (CPU) -> rb -> ch -> oif -> oport -> (outer of AIO) * For sampling rate converter device: * (CPU) -> rb -> ch -> oif -> (HW SRC) -> iif -> och -> orb -> (CPU) */ struct uniphier_aio_swmap { … }; struct uniphier_aio_spec { … }; struct uniphier_aio_pll { … }; struct uniphier_aio_chip_spec { … }; struct uniphier_aio_sub { … }; struct uniphier_aio { … }; struct uniphier_aio_chip { … }; static inline struct uniphier_aio *uniphier_priv(struct snd_soc_dai *dai) { … } int uniphier_aiodma_soc_register_platform(struct platform_device *pdev); extern const struct snd_compress_ops uniphier_aio_compress_ops; int uniphier_aio_probe(struct platform_device *pdev); void uniphier_aio_remove(struct platform_device *pdev); extern const struct snd_soc_dai_ops uniphier_aio_i2s_ld11_ops; extern const struct snd_soc_dai_ops uniphier_aio_i2s_pxs2_ops; extern const struct snd_soc_dai_ops uniphier_aio_spdif_ld11_ops; extern const struct snd_soc_dai_ops uniphier_aio_spdif_ld11_ops2; extern const struct snd_soc_dai_ops uniphier_aio_spdif_pxs2_ops; extern const struct snd_soc_dai_ops uniphier_aio_spdif_pxs2_ops2; u64 aio_rb_cnt(struct uniphier_aio_sub *sub); u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub); u64 aio_rb_space(struct uniphier_aio_sub *sub); u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub); void aio_iecout_set_enable(struct uniphier_aio_chip *chip, bool enable); int aio_chip_set_pll(struct uniphier_aio_chip *chip, int pll_id, unsigned int freq); void aio_chip_init(struct uniphier_aio_chip *chip); int aio_init(struct uniphier_aio_sub *sub); void aio_port_reset(struct uniphier_aio_sub *sub); int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through, const struct snd_pcm_hw_params *params); void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable); int aio_port_get_volume(struct uniphier_aio_sub *sub); void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol); int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through); int aio_oport_set_stream_type(struct uniphier_aio_sub *sub, enum IEC61937_PC pc); void aio_src_reset(struct uniphier_aio_sub *sub); int aio_src_set_param(struct uniphier_aio_sub *sub, const struct snd_pcm_hw_params *params); int aio_srcif_set_param(struct uniphier_aio_sub *sub); int aio_srcch_set_param(struct uniphier_aio_sub *sub); void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable); int aiodma_ch_set_param(struct uniphier_aio_sub *sub); void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable); int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th); int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end, int period); void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size, int period); bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub); void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub); #endif /* SND_UNIPHIER_AIO_H__ */
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