/* SPDX-License-Identifier: GPL-2.0-only */ /* * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver * * Copyright (C) 2016 Intel Corp * Authors: Sailaja Bandarupalli <[email protected]> * Ramesh Babu K V <[email protected]> * Vaibhav Agarwal <[email protected]> * Jerome Anand <[email protected]> * Aravind Siddappaji <[email protected]> * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ #ifndef __INTEL_HDMI_LPE_AUDIO_H #define __INTEL_HDMI_LPE_AUDIO_H #define HAD_MIN_CHANNEL … #define HAD_MAX_CHANNEL … #define HAD_NUM_OF_RING_BUFS … /* max 20bit address, aligned to 64 */ #define HAD_MAX_BUFFER … #define HAD_DEFAULT_BUFFER … #define HAD_MAX_PERIODS … #define HAD_MIN_PERIODS … #define HAD_MAX_PERIOD_BYTES … #define HAD_MIN_PERIOD_BYTES … #define HAD_FIFO_SIZE … #define MAX_SPEAKERS … #define AUD_SAMPLE_RATE_32 … #define AUD_SAMPLE_RATE_44_1 … #define AUD_SAMPLE_RATE_48 … #define AUD_SAMPLE_RATE_88_2 … #define AUD_SAMPLE_RATE_96 … #define AUD_SAMPLE_RATE_176_4 … #define AUD_SAMPLE_RATE_192 … #define HAD_MIN_RATE … #define HAD_MAX_RATE … #define DIS_SAMPLE_RATE_25_2 … #define DIS_SAMPLE_RATE_27 … #define DIS_SAMPLE_RATE_54 … #define DIS_SAMPLE_RATE_74_25 … #define DIS_SAMPLE_RATE_148_5 … #define HAD_REG_WIDTH … #define HAD_MAX_DIP_WORDS … /* DP Link Rates */ #define DP_2_7_GHZ … #define DP_1_62_GHZ … /* Maud Values */ #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL … #define HAD_MAX_RATE_DP_2_7_MAUD_VAL … #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL … #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL … #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL … #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL … #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL … #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL … #define HAD_MAX_RATE_DP_1_62_MAUD_VAL … /* Naud Value */ #define DP_NAUD_VAL … /* HDMI Controller register offsets - audio domain common */ /* Base address for below regs = 0x65000 */ enum hdmi_ctrl_reg_offset_common { … }; /* HDMI controller register offsets */ enum hdmi_ctrl_reg_offset { … }; /* Audio configuration */ aud_cfg; #define AUD_CONFIG_VALID_BIT … #define AUD_CONFIG_DP_MODE … #define AUD_CONFIG_CH_MASK … #define LAYOUT0 … #define LAYOUT1 … /* Audio Channel Status 0 Attributes */ aud_ch_status_0; /* samp_freq values - Sampling rate as per IEC60958 Ver 3 */ #define CH_STATUS_MAP_32KHZ … #define CH_STATUS_MAP_44KHZ … #define CH_STATUS_MAP_48KHZ … #define CH_STATUS_MAP_88KHZ … #define CH_STATUS_MAP_96KHZ … #define CH_STATUS_MAP_176KHZ … #define CH_STATUS_MAP_192KHZ … /* Audio Channel Status 1 Attributes */ aud_ch_status_1; #define MAX_SMPL_WIDTH_20 … #define MAX_SMPL_WIDTH_24 … #define SMPL_WIDTH_16BITS … #define SMPL_WIDTH_24BITS … /* CTS register */ aud_hdmi_cts; /* N register */ aud_hdmi_n_enable; /* Audio Buffer configurations */ aud_buf_config; #define FIFO_THRESHOLD … #define DMA_FIFO_THRESHOLD … /* Audio Sample Swapping offset */ aud_buf_ch_swap; #define SWAP_LFE_CENTER … /* Address for Audio Buffer */ aud_buf_addr; #define AUD_BUF_VALID … #define AUD_BUF_INTR_EN … /* Length of Audio Buffer */ aud_buf_len; /* Audio Control State Register offset */ aud_ctrl_st; /* Audio HDMI Widget Data Island Packet offset */ aud_info_frame1; #define HDMI_INFO_FRAME_WORD1 … #define DP_INFO_FRAME_WORD1 … /* DIP frame 2 */ aud_info_frame2; /* DIP frame 3 */ aud_info_frame3; #define VALID_DIP_WORDS … /* AUD_HDMI_STATUS bits */ #define HDMI_AUDIO_UNDERRUN … #define HDMI_AUDIO_BUFFER_DONE … /* AUD_HDMI_STATUS register mask */ #define AUD_HDMI_STATUS_MASK_UNDERRUN … #define AUD_HDMI_STATUS_MASK_SRDBG … #define AUD_HDMI_STATUSG_MASK_FUNCRST … #endif
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