// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2023 Linaro Ltd. * Author: Peter Griffin <[email protected]> * * Common Clock Framework support for GS101. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/google,gs101.h> #include "clk.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP … #define CLKS_NR_APM … #define CLKS_NR_HSI0 … #define CLKS_NR_HSI2 … #define CLKS_NR_MISC … #define CLKS_NR_PERIC0 … #define CLKS_NR_PERIC1 … /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x1e080000) */ #define PLL_LOCKTIME_PLL_SHARED0 … #define PLL_LOCKTIME_PLL_SHARED1 … #define PLL_LOCKTIME_PLL_SHARED2 … #define PLL_LOCKTIME_PLL_SHARED3 … #define PLL_LOCKTIME_PLL_SPARE … #define PLL_CON0_PLL_SHARED0 … #define PLL_CON1_PLL_SHARED0 … #define PLL_CON2_PLL_SHARED0 … #define PLL_CON3_PLL_SHARED0 … #define PLL_CON4_PLL_SHARED0 … #define PLL_CON0_PLL_SHARED1 … #define PLL_CON1_PLL_SHARED1 … #define PLL_CON2_PLL_SHARED1 … #define PLL_CON3_PLL_SHARED1 … #define PLL_CON4_PLL_SHARED1 … #define PLL_CON0_PLL_SHARED2 … #define PLL_CON1_PLL_SHARED2 … #define PLL_CON2_PLL_SHARED2 … #define PLL_CON3_PLL_SHARED2 … #define PLL_CON4_PLL_SHARED2 … #define PLL_CON0_PLL_SHARED3 … #define PLL_CON1_PLL_SHARED3 … #define PLL_CON2_PLL_SHARED3 … #define PLL_CON3_PLL_SHARED3 … #define PLL_CON4_PLL_SHARED3 … #define PLL_CON0_PLL_SPARE … #define PLL_CON1_PLL_SPARE … #define PLL_CON2_PLL_SPARE … #define PLL_CON3_PLL_SPARE … #define PLL_CON4_PLL_SPARE … #define CMU_CMU_TOP_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 … #define CMU_HCHGEN_CLKMUX_CMU_BOOST … #define CMU_HCHGEN_CLKMUX_TOP_BOOST … #define CMU_HCHGEN_CLKMUX … #define POWER_FAIL_DETECT_PLL … #define EARLY_WAKEUP_FORCED_0_ENABLE … #define EARLY_WAKEUP_FORCED_1_ENABLE … #define EARLY_WAKEUP_APM_CTRL … #define EARLY_WAKEUP_CLUSTER0_CTRL … #define EARLY_WAKEUP_DPU_CTRL … #define EARLY_WAKEUP_CSIS_CTRL … #define EARLY_WAKEUP_APM_DEST … #define EARLY_WAKEUP_CLUSTER0_DEST … #define EARLY_WAKEUP_DPU_DEST … #define EARLY_WAKEUP_CSIS_DEST … #define EARLY_WAKEUP_SW_TRIG_APM … #define EARLY_WAKEUP_SW_TRIG_APM_SET … #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR … #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 … #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET … #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR … #define EARLY_WAKEUP_SW_TRIG_DPU … #define EARLY_WAKEUP_SW_TRIG_DPU_SET … #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR … #define EARLY_WAKEUP_SW_TRIG_CSIS … #define EARLY_WAKEUP_SW_TRIG_CSIS_SET … #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR … #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS … #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 … #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST … #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 … #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS … #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS … #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D … #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL … #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA … #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD … #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB … #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 … #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 … #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC … #define CLK_CON_MUX_MUX_CLKCMU_HPM … #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC … #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD … #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG … #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD … #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS … #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS … #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC … #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC … #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC … #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP … #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS … #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS … #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP … #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS … #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 … #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF … #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS … #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU … #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL … #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART … #define CLK_CON_MUX_MUX_CMU_CMUREF … #define CLK_CON_DIV_CLKCMU_BO_BUS … #define CLK_CON_DIV_CLKCMU_BUS0_BUS … #define CLK_CON_DIV_CLKCMU_BUS1_BUS … #define CLK_CON_DIV_CLKCMU_BUS2_BUS … #define CLK_CON_DIV_CLKCMU_CIS_CLK0 … #define CLK_CON_DIV_CLKCMU_CIS_CLK1 … #define CLK_CON_DIV_CLKCMU_CIS_CLK2 … #define CLK_CON_DIV_CLKCMU_CIS_CLK3 … #define CLK_CON_DIV_CLKCMU_CIS_CLK4 … #define CLK_CON_DIV_CLKCMU_CIS_CLK5 … #define CLK_CON_DIV_CLKCMU_CIS_CLK6 … #define CLK_CON_DIV_CLKCMU_CIS_CLK7 … #define CLK_CON_DIV_CLKCMU_CORE_BUS … #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG … #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH … #define CLK_CON_DIV_CLKCMU_CSIS_BUS … #define CLK_CON_DIV_CLKCMU_DISP_BUS … #define CLK_CON_DIV_CLKCMU_DNS_BUS … #define CLK_CON_DIV_CLKCMU_DPU_BUS … #define CLK_CON_DIV_CLKCMU_EH_BUS … #define CLK_CON_DIV_CLKCMU_G2D_G2D … #define CLK_CON_DIV_CLKCMU_G2D_MSCL … #define CLK_CON_DIV_CLKCMU_G3AA_G3AA … #define CLK_CON_DIV_CLKCMU_G3D_BUSD … #define CLK_CON_DIV_CLKCMU_G3D_GLB … #define CLK_CON_DIV_CLKCMU_G3D_SWITCH … #define CLK_CON_DIV_CLKCMU_GDC_GDC0 … #define CLK_CON_DIV_CLKCMU_GDC_GDC1 … #define CLK_CON_DIV_CLKCMU_GDC_SCSC … #define CLK_CON_DIV_CLKCMU_HPM … #define CLK_CON_DIV_CLKCMU_HSI0_BUS … #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC … #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD … #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG … #define CLK_CON_DIV_CLKCMU_HSI1_BUS … #define CLK_CON_DIV_CLKCMU_HSI1_PCIE … #define CLK_CON_DIV_CLKCMU_HSI2_BUS … #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD … #define CLK_CON_DIV_CLKCMU_HSI2_PCIE … #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD … #define CLK_CON_DIV_CLKCMU_IPP_BUS … #define CLK_CON_DIV_CLKCMU_ITP_BUS … #define CLK_CON_DIV_CLKCMU_MCSC_ITSC … #define CLK_CON_DIV_CLKCMU_MCSC_MCSC … #define CLK_CON_DIV_CLKCMU_MFC_MFC … #define CLK_CON_DIV_CLKCMU_MIF_BUSP … #define CLK_CON_DIV_CLKCMU_MISC_BUS … #define CLK_CON_DIV_CLKCMU_MISC_SSS … #define CLK_CON_DIV_CLKCMU_OTP … #define CLK_CON_DIV_CLKCMU_PDP_BUS … #define CLK_CON_DIV_CLKCMU_PDP_VRA … #define CLK_CON_DIV_CLKCMU_PERIC0_BUS … #define CLK_CON_DIV_CLKCMU_PERIC0_IP … #define CLK_CON_DIV_CLKCMU_PERIC1_BUS … #define CLK_CON_DIV_CLKCMU_PERIC1_IP … #define CLK_CON_DIV_CLKCMU_TNR_BUS … #define CLK_CON_DIV_CLKCMU_TPU_BUS … #define CLK_CON_DIV_CLKCMU_TPU_TPU … #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL … #define CLK_CON_DIV_CLKCMU_TPU_UART … #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST … #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF … #define CLK_CON_DIV_PLL_SHARED0_DIV2 … #define CLK_CON_DIV_PLL_SHARED0_DIV3 … #define CLK_CON_DIV_PLL_SHARED0_DIV4 … #define CLK_CON_DIV_PLL_SHARED0_DIV5 … #define CLK_CON_DIV_PLL_SHARED1_DIV2 … #define CLK_CON_DIV_PLL_SHARED1_DIV3 … #define CLK_CON_DIV_PLL_SHARED1_DIV4 … #define CLK_CON_DIV_PLL_SHARED2_DIV2 … #define CLK_CON_DIV_PLL_SHARED3_DIV2 … #define CLK_CON_GAT_CLKCMU_BUS0_BOOST … #define CLK_CON_GAT_CLKCMU_BUS1_BOOST … #define CLK_CON_GAT_CLKCMU_BUS2_BOOST … #define CLK_CON_GAT_CLKCMU_CORE_BOOST … #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST … #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST … #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST … #define CLK_CON_GAT_CLKCMU_MIF_BOOST … #define CLK_CON_GAT_CLKCMU_MIF_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS … #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 … #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 … #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST … #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS … #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS … #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D … #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL … #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA … #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD … #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB … #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 … #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 … #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC … #define CLK_CON_GAT_GATE_CLKCMU_HPM … #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC … #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD … #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG … #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE … #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS … #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD … #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE … #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD … #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS … #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS … #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC … #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC … #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC … #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP … #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS … #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS … #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA … #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP … #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP … #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS … #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF … #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS … #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU … #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL … #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART … #define DMYQCH_CON_CMU_TOP_CMUREF_QCH … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 … #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 … #define DMYQCH_CON_OTP_QCH … #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP … #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP … #define MIFMIRROR_QUEUE_CTRL_REG … #define MIFMIRROR_QUEUE_ENTRY0 … #define MIFMIRROR_QUEUE_ENTRY1 … #define MIFMIRROR_QUEUE_ENTRY2 … #define MIFMIRROR_QUEUE_ENTRY3 … #define MIFMIRROR_QUEUE_ENTRY4 … #define MIFMIRROR_QUEUE_ENTRY5 … #define MIFMIRROR_QUEUE_ENTRY6 … #define MIFMIRROR_QUEUE_ENTRY7 … #define MIFMIRROR_QUEUE_BUSY … #define GENERALIO_ACD_CHANNEL_0 … #define GENERALIO_ACD_CHANNEL_1 … #define GENERALIO_ACD_CHANNEL_2 … #define GENERALIO_ACD_CHANNEL_3 … #define GENERALIO_ACD_MASK … static const unsigned long cmu_top_clk_regs[] __initconst = …; static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_TOP */ PNAME(mout_pll_shared0_p) = …; PNAME(mout_pll_shared1_p) = …; PNAME(mout_pll_shared2_p) = …; PNAME(mout_pll_shared3_p) = …; PNAME(mout_pll_spare_p) = …; PNAME(mout_cmu_bo_bus_p) = …; PNAME(mout_cmu_bus0_bus_p) = …; PNAME(mout_cmu_bus1_bus_p) = …; PNAME(mout_cmu_bus2_bus_p) = …; PNAME(mout_cmu_cis_clk0_7_p) = …; PNAME(mout_cmu_cmu_boost_p) = …; PNAME(mout_cmu_cmu_boost_option1_p) = …; PNAME(mout_cmu_core_bus_p) = …; PNAME(mout_cmu_cpucl0_dbg_p) = …; PNAME(mout_cmu_cpucl0_switch_p) = …; PNAME(mout_cmu_cpucl1_switch_p) = …; PNAME(mout_cmu_cpucl2_switch_p) = …; PNAME(mout_cmu_csis_bus_p) = …; PNAME(mout_cmu_disp_bus_p) = …; PNAME(mout_cmu_dns_bus_p) = …; PNAME(mout_cmu_dpu_p) = …; PNAME(mout_cmu_eh_bus_p) = …; PNAME(mout_cmu_g2d_g2d_p) = …; PNAME(mout_cmu_g2d_mscl_p) = …; PNAME(mout_cmu_g3aa_g3aa_p) = …; PNAME(mout_cmu_g3d_busd_p) = …; PNAME(mout_cmu_g3d_glb_p) = …; PNAME(mout_cmu_g3d_switch_p) = …; PNAME(mout_cmu_gdc_gdc0_p) = …; PNAME(mout_cmu_gdc_gdc1_p) = …; PNAME(mout_cmu_gdc_scsc_p) = …; PNAME(mout_cmu_hpm_p) = …; PNAME(mout_cmu_hsi0_bus_p) = …; PNAME(mout_cmu_hsi0_dpgtc_p) = …; PNAME(mout_cmu_hsi0_usb31drd_p) = …; PNAME(mout_cmu_hsi0_usbdpdbg_p) = …; PNAME(mout_cmu_hsi1_bus_p) = …; PNAME(mout_cmu_hsi1_pcie_p) = …; PNAME(mout_cmu_hsi2_bus_p) = …; PNAME(mout_cmu_hsi2_mmc_card_p) = …; PNAME(mout_cmu_hsi2_pcie0_p) = …; PNAME(mout_cmu_hsi2_ufs_embd_p) = …; PNAME(mout_cmu_ipp_bus_p) = …; PNAME(mout_cmu_itp_bus_p) = …; PNAME(mout_cmu_mcsc_itsc_p) = …; PNAME(mout_cmu_mcsc_mcsc_p) = …; PNAME(mout_cmu_mfc_mfc_p) = …; PNAME(mout_cmu_mif_busp_p) = …; PNAME(mout_cmu_mif_switch_p) = …; PNAME(mout_cmu_misc_bus_p) = …; PNAME(mout_cmu_misc_sss_p) = …; PNAME(mout_cmu_pdp_bus_p) = …; PNAME(mout_cmu_pdp_vra_p) = …; PNAME(mout_cmu_peric0_bus_p) = …; PNAME(mout_cmu_peric0_ip_p) = …; PNAME(mout_cmu_peric1_bus_p) = …; PNAME(mout_cmu_peric1_ip_p) = …; PNAME(mout_cmu_tnr_bus_p) = …; PNAME(mout_cmu_top_boost_option1_p) = …; PNAME(mout_cmu_top_cmuref_p) = …; PNAME(mout_cmu_tpu_bus_p) = …; PNAME(mout_cmu_tpu_tpu_p) = …; PNAME(mout_cmu_tpu_tpuctl_p) = …; PNAME(mout_cmu_tpu_uart_p) = …; PNAME(mout_cmu_cmuref_p) = …; /* * Register name to clock name mangling strategy used in this file * * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu * * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC */ static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = …; static const struct samsung_div_clock cmu_top_div_clks[] __initconst = …; static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = …; static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = …; static const struct samsung_cmu_info top_cmu_info __initconst = …; static void __init gs101_cmu_top_init(struct device_node *np) { … } /* Register CMU_TOP early, as it's a dependency for other early domains */ CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", gs101_cmu_top_init); /* ---- CMU_APM ------------------------------------------------------------- */ /* Register Offset definitions for CMU_APM (0x17400000) */ #define APM_CMU_APM_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 … #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC … #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC … #define CLK_CON_DIV_DIV_CLK_APM_BOOST … #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART … #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI … #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART … #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 … #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 … #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 … #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 … #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK … #define PCH_CON_LHM_AXI_G_SWD_PCH … #define PCH_CON_LHM_AXI_P_AOCAPM_PCH … #define PCH_CON_LHM_AXI_P_APM_PCH … #define PCH_CON_LHS_AXI_D_APM_PCH … #define PCH_CON_LHS_AXI_G_DBGCORE_PCH … #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH … #define QCH_CON_APBIF_GPIO_ALIVE_QCH … #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH … #define QCH_CON_APBIF_PMU_ALIVE_QCH … #define QCH_CON_APBIF_RTC_QCH … #define QCH_CON_APBIF_TRTC_QCH … #define QCH_CON_APM_CMU_APM_QCH … #define QCH_CON_APM_USI0_UART_QCH … #define QCH_CON_APM_USI0_USI_QCH … #define QCH_CON_APM_USI1_UART_QCH … #define QCH_CON_D_TZPC_APM_QCH … #define QCH_CON_GPC_APM_QCH … #define QCH_CON_GREBEINTEGRATION_QCH_DBG … #define QCH_CON_GREBEINTEGRATION_QCH_GREBE … #define QCH_CON_INTMEM_QCH … #define QCH_CON_LHM_AXI_G_SWD_QCH … #define QCH_CON_LHM_AXI_P_AOCAPM_QCH … #define QCH_CON_LHM_AXI_P_APM_QCH … #define QCH_CON_LHS_AXI_D_APM_QCH … #define QCH_CON_LHS_AXI_G_DBGCORE_QCH … #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH … #define QCH_CON_MAILBOX_APM_AOC_QCH … #define QCH_CON_MAILBOX_APM_AP_QCH … #define QCH_CON_MAILBOX_APM_GSA_QCH … #define QCH_CON_MAILBOX_APM_SWD_QCH … #define QCH_CON_MAILBOX_APM_TPU_QCH … #define QCH_CON_MAILBOX_AP_AOC_QCH … #define QCH_CON_MAILBOX_AP_DBGCORE_QCH … #define QCH_CON_PMU_INTR_GEN_QCH … #define QCH_CON_ROM_CRC32_HOST_QCH … #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE … #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG … #define QCH_CON_SPEEDY_APM_QCH … #define QCH_CON_SPEEDY_SUB_APM_QCH … #define QCH_CON_SSMT_D_APM_QCH … #define QCH_CON_SSMT_G_DBGCORE_QCH … #define QCH_CON_SS_DBGCORE_QCH_DBG … #define QCH_CON_SS_DBGCORE_QCH_GREBE … #define QCH_CON_SYSMMU_D_APM_QCH … #define QCH_CON_SYSREG_APM_QCH … #define QCH_CON_UASC_APM_QCH … #define QCH_CON_UASC_DBGCORE_QCH … #define QCH_CON_UASC_G_SWD_QCH … #define QCH_CON_UASC_P_AOCAPM_QCH … #define QCH_CON_UASC_P_APM_QCH … #define QCH_CON_WDT_APM_QCH … #define QUEUE_CTRL_REG_BLK_APM_CMU_APM … static const unsigned long apm_clk_regs[] __initconst = …; PNAME(mout_apm_func_p) = …; PNAME(mout_apm_funcsrc_p) = …; static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = …; static const struct samsung_mux_clock apm_mux_clks[] __initconst = …; static const struct samsung_div_clock apm_div_clks[] __initconst = …; static const struct samsung_gate_clock apm_gate_clks[] __initconst = …; static const struct samsung_cmu_info apm_cmu_info __initconst = …; /* ---- CMU_HSI0 ------------------------------------------------------------ */ /* Register Offset definitions for CMU_HSI0 (0x11000000) */ #define PLL_LOCKTIME_PLL_USB … #define PLL_CON0_PLL_USB … #define PLL_CON1_PLL_USB … #define PLL_CON2_PLL_USB … #define PLL_CON3_PLL_USB … #define PLL_CON4_PLL_USB … #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER … #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER … #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER … #define HSI0_CMU_HSI0_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 … #define CLK_CON_MUX_MUX_CLK_HSI0_BUS … #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF … #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD … #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD … #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 … #define CLK_CON_GAT_CLK_HSI0_ALT … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK … #define DMYQCH_CON_USB31DRD_QCH … #define DMYQCH_CON_USB31DRD_QCH_REF … #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH … #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH … #define PCH_CON_LHM_AXI_P_HSI0_PCH … #define PCH_CON_LHS_ACEL_D_HSI0_PCH … #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH … #define QCH_CON_DP_LINK_QCH_GTC_CLK … #define QCH_CON_DP_LINK_QCH_PCLK … #define QCH_CON_D_TZPC_HSI0_QCH … #define QCH_CON_ETR_MIU_QCH_ACLK … #define QCH_CON_ETR_MIU_QCH_PCLK … #define QCH_CON_GPC_HSI0_QCH … #define QCH_CON_HSI0_CMU_HSI0_QCH … #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH … #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH … #define QCH_CON_LHM_AXI_P_HSI0_QCH … #define QCH_CON_LHS_ACEL_D_HSI0_QCH … #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH … #define QCH_CON_PPMU_HSI0_AOC_QCH … #define QCH_CON_PPMU_HSI0_BUS0_QCH … #define QCH_CON_SSMT_USB_QCH … #define QCH_CON_SYSMMU_USB_QCH … #define QCH_CON_SYSREG_HSI0_QCH … #define QCH_CON_UASC_HSI0_CTRL_QCH … #define QCH_CON_UASC_HSI0_LINK_QCH … #define QCH_CON_USB31DRD_QCH_APB … #define QCH_CON_USB31DRD_QCH_DBG … #define QCH_CON_USB31DRD_QCH_PCS … #define QCH_CON_USB31DRD_QCH_SLV_CTRL … #define QCH_CON_USB31DRD_QCH_SLV_LINK … #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 … static const unsigned long hsi0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_HSI0 */ PNAME(mout_pll_usb_p) = …; PNAME(mout_hsi0_alt_user_p) = …; PNAME(mout_hsi0_bus_user_p) = …; PNAME(mout_hsi0_dpgtc_user_p) = …; PNAME(mout_hsi0_tcxo_user_p) = …; PNAME(mout_hsi0_usb20_user_p) = …; PNAME(mout_hsi0_usb31drd_user_p) = …; PNAME(mout_hsi0_usbdpdbg_user_p) = …; PNAME(mout_hsi0_bus_p) = …; PNAME(mout_hsi0_usb20_ref_p) = …; PNAME(mout_hsi0_usb31drd_p) = …; static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = …; static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = …; static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = …; static const struct samsung_div_clock hsi0_div_clks[] __initconst = …; static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = …; static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = …; static const struct samsung_cmu_info hsi0_cmu_info __initconst = …; /* ---- CMU_HSI2 ------------------------------------------------------------ */ /* Register Offset definitions for CMU_HSI2 (0x14400000) */ #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER … #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER … #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER … #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER … #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER … #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER … #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER … #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER … #define HSI2_CMU_HSI2_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK … #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 … #define PCH_CON_LHM_AXI_P_HSI2_PCH … #define PCH_CON_LHS_ACEL_D_HSI2_PCH … #define QCH_CON_D_TZPC_HSI2_QCH … #define QCH_CON_GPC_HSI2_QCH … #define QCH_CON_GPIO_HSI2_QCH … #define QCH_CON_HSI2_CMU_HSI2_QCH … #define QCH_CON_LHM_AXI_P_HSI2_QCH … #define QCH_CON_LHS_ACEL_D_HSI2_QCH … #define QCH_CON_MMC_CARD_QCH … #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 … #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 … #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 … #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 … #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 … #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 … #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB … #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB … #define QCH_CON_PCIE_GEN4_1_QCH_UDBG … #define QCH_CON_PCIE_IA_GEN4A_1_QCH … #define QCH_CON_PCIE_IA_GEN4B_1_QCH … #define QCH_CON_PPMU_HSI2_QCH … #define QCH_CON_QE_MMC_CARD_HSI2_QCH … #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH … #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH … #define QCH_CON_QE_UFS_EMBD_HSI2_QCH … #define QCH_CON_SSMT_HSI2_QCH … #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH … #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH … #define QCH_CON_SYSMMU_HSI2_QCH … #define QCH_CON_SYSREG_HSI2_QCH … #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH … #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH … #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH … #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH … #define QCH_CON_UFS_EMBD_QCH … #define QCH_CON_UFS_EMBD_QCH_FMP … #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 … static const unsigned long cmu_hsi2_clk_regs[] __initconst = …; PNAME(mout_hsi2_bus_user_p) = …; PNAME(mout_hsi2_mmc_card_user_p) = …; PNAME(mout_hsi2_pcie_user_p) = …; PNAME(mout_hsi2_ufs_embd_user_p) = …; static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = …; static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = …; static const struct samsung_cmu_info hsi2_cmu_info __initconst = …; /* ---- CMU_MISC ------------------------------------------------------------ */ /* Register Offset definitions for CMU_MISC (0x10010000) */ #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER … #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER … #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER … #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER … #define MISC_CMU_MISC_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 … #define CLK_CON_MUX_MUX_CLK_MISC_GIC … #define CLK_CON_DIV_DIV_CLK_MISC_BUSP … #define CLK_CON_DIV_DIV_CLK_MISC_GIC … #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK … #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK … #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK … #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK … #define DMYQCH_CON_PPMU_DMA_QCH … #define DMYQCH_CON_PUF_QCH … #define PCH_CON_LHM_AXI_D_SSS_PCH … #define PCH_CON_LHM_AXI_P_GIC_PCH … #define PCH_CON_LHM_AXI_P_MISC_PCH … #define PCH_CON_LHS_ACEL_D_MISC_PCH … #define PCH_CON_LHS_AST_IRI_GICCPU_PCH … #define PCH_CON_LHS_AXI_D_SSS_PCH … #define QCH_CON_ADM_AHB_SSS_QCH … #define QCH_CON_DIT_QCH … #define QCH_CON_GIC_QCH … #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH … #define QCH_CON_LHM_AXI_D_SSS_QCH … #define QCH_CON_LHM_AXI_P_GIC_QCH … #define QCH_CON_LHM_AXI_P_MISC_QCH … #define QCH_CON_LHS_ACEL_D_MISC_QCH … #define QCH_CON_LHS_AST_IRI_GICCPU_QCH … #define QCH_CON_LHS_AXI_D_SSS_QCH … #define QCH_CON_MCT_QCH … #define QCH_CON_MISC_CMU_MISC_QCH … #define QCH_CON_OTP_CON_BIRA_QCH … #define QCH_CON_OTP_CON_BISR_QCH … #define QCH_CON_OTP_CON_TOP_QCH … #define QCH_CON_PDMA_QCH … #define QCH_CON_PPMU_MISC_QCH … #define QCH_CON_QE_DIT_QCH … #define QCH_CON_QE_PDMA_QCH … #define QCH_CON_QE_PPMU_DMA_QCH … #define QCH_CON_QE_RTIC_QCH … #define QCH_CON_QE_SPDMA_QCH … #define QCH_CON_QE_SSS_QCH … #define QCH_CON_RTIC_QCH … #define QCH_CON_SPDMA_QCH … #define QCH_CON_SSMT_DIT_QCH … #define QCH_CON_SSMT_PDMA_QCH … #define QCH_CON_SSMT_PPMU_DMA_QCH … #define QCH_CON_SSMT_RTIC_QCH … #define QCH_CON_SSMT_SPDMA_QCH … #define QCH_CON_SSMT_SSS_QCH … #define QCH_CON_SSS_QCH … #define QCH_CON_SYSMMU_MISC_QCH … #define QCH_CON_SYSMMU_SSS_QCH … #define QCH_CON_SYSREG_MISC_QCH … #define QCH_CON_TMU_SUB_QCH … #define QCH_CON_TMU_TOP_QCH … #define QCH_CON_WDT_CLUSTER0_QCH … #define QCH_CON_WDT_CLUSTER1_QCH … #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC … static const unsigned long misc_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_MISC */ PNAME(mout_misc_bus_user_p) = …; PNAME(mout_misc_sss_user_p) = …; PNAME(mout_misc_gic_p) = …; static const struct samsung_mux_clock misc_mux_clks[] __initconst = …; static const struct samsung_div_clock misc_div_clks[] __initconst = …; static const struct samsung_gate_clock misc_gate_clks[] __initconst = …; static const struct samsung_cmu_info misc_cmu_info __initconst = …; static void __init gs101_cmu_misc_init(struct device_node *np) { … } /* Register CMU_MISC early, as it's needed for MCT timer */ CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", gs101_cmu_misc_init); /* ---- CMU_PERIC0 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER … #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 … #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI … #define CLK_CON_BUF_CLKBUF_PERIC0_IP … #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK … #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 … #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 … #define PCH_CON_LHM_AXI_P_PERIC0_PCH … #define QCH_CON_D_TZPC_PERIC0_QCH … #define QCH_CON_GPC_PERIC0_QCH … #define QCH_CON_GPIO_PERIC0_QCH … #define QCH_CON_LHM_AXI_P_PERIC0_QCH … #define QCH_CON_PERIC0_CMU_PERIC0_QCH … #define QCH_CON_PERIC0_TOP0_QCH_I3C1 … #define QCH_CON_PERIC0_TOP0_QCH_I3C2 … #define QCH_CON_PERIC0_TOP0_QCH_I3C3 … #define QCH_CON_PERIC0_TOP0_QCH_I3C4 … #define QCH_CON_PERIC0_TOP0_QCH_I3C5 … #define QCH_CON_PERIC0_TOP0_QCH_I3C6 … #define QCH_CON_PERIC0_TOP0_QCH_I3C7 … #define QCH_CON_PERIC0_TOP0_QCH_I3C8 … #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI … #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI … #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART … #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART … #define QCH_CON_SYSREG_PERIC0_QCH … #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 … static const unsigned long peric0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC0 */ PNAME(mout_peric0_bus_user_p) = …; PNAME(mout_peric0_i3c_user_p) = …; PNAME(mout_peric0_usi0_uart_user_p) = …; PNAME(mout_peric0_usi_usi_user_p) = …; static const struct samsung_mux_clock peric0_mux_clks[] __initconst = …; static const struct samsung_div_clock peric0_div_clks[] __initconst = …; static const struct samsung_gate_clock peric0_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric0_cmu_info __initconst = …; /* ---- CMU_PERIC1 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER … #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER … #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION … #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 … #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI … #define CLK_CON_BUF_CLKBUF_PERIC1_IP … #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK … #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK … #define DMYQCH_CON_PERIC1_TOP0_QCH_S … #define PCH_CON_LHM_AXI_P_PERIC1_PCH … #define QCH_CON_D_TZPC_PERIC1_QCH … #define QCH_CON_GPC_PERIC1_QCH … #define QCH_CON_GPIO_PERIC1_QCH … #define QCH_CON_LHM_AXI_P_PERIC1_QCH … #define QCH_CON_PERIC1_CMU_PERIC1_QCH … #define QCH_CON_PERIC1_TOP0_QCH_I3C0 … #define QCH_CON_PERIC1_TOP0_QCH_PWM … #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI … #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI … #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI … #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI … #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI … #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI … #define QCH_CON_SYSREG_PERIC1_QCH … #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 … static const unsigned long peric1_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC1 */ PNAME(mout_peric1_bus_user_p) = …; PNAME(mout_peric1_nonbususer_p) = …; static const struct samsung_mux_clock peric1_mux_clks[] __initconst = …; static const struct samsung_div_clock peric1_div_clks[] __initconst = …; static const struct samsung_gate_clock peric1_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric1_cmu_info __initconst = …; /* ---- platform_driver ----------------------------------------------------- */ static int __init gs101_cmu_probe(struct platform_device *pdev) { … } static const struct of_device_id gs101_cmu_of_match[] = …; static struct platform_driver gs101_cmu_driver __refdata = …; static int __init gs101_cmu_init(void) { … } core_initcall(gs101_cmu_init);
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