linux/drivers/clk/socfpga/clk-gate.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright 2011-2012 Calxeda, Inc.
 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
 *
 * Based from clk-highbank.c
 */
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/regmap.h>

#include "clk.h"

#define SOCFPGA_L4_MP_CLK …
#define SOCFPGA_L4_SP_CLK …
#define SOCFPGA_NAND_CLK …
#define SOCFPGA_NAND_X_CLK …
#define SOCFPGA_MMC_CLK …
#define SOCFPGA_GPIO_DB_CLK_OFFSET …

#define to_socfpga_gate_clk(p) …

/* SDMMC Group for System Manager defines */
#define SYSMGR_SDMMCGRP_CTRL_OFFSET …

static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
{ … }

static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
{ … }

static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk)
{ … }

static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
					     unsigned long parent_rate)
{ … }


static int socfpga_clk_determine_rate(struct clk_hw *hwclk,
				      struct clk_rate_request *req)
{ … }

static struct clk_ops gateclk_ops = …;

void __init socfpga_gate_init(struct device_node *node)
{ … }