/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. * https://www.samsung.com * Copyright (c) 2017-2022 Tesla, Inc. * https://www.tesla.com * * The constants defined in this header are being used in dts * and fsd platform driver. */ #ifndef _DT_BINDINGS_CLOCK_FSD_H #define _DT_BINDINGS_CLOCK_FSD_H /* CMU */ #define DOUT_CMU_PLL_SHARED0_DIV4 … #define DOUT_CMU_PERIC_SHARED1DIV36 … #define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK … #define DOUT_CMU_PERIC_SHARED0DIV20 … #define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK … #define DOUT_CMU_PLL_SHARED0_DIV6 … #define DOUT_CMU_FSYS0_SHARED1DIV4 … #define DOUT_CMU_FSYS0_SHARED0DIV4 … #define DOUT_CMU_FSYS1_SHARED0DIV8 … #define DOUT_CMU_FSYS1_SHARED0DIV4 … #define CMU_CPUCL_SWITCH_GATE … #define DOUT_CMU_IMEM_TCUCLK … #define DOUT_CMU_IMEM_ACLK … #define DOUT_CMU_IMEM_DMACLK … #define GAT_CMU_FSYS0_SHARED0DIV4 … #define CMU_NR_CLK … /* PERIC */ #define PERIC_SCLK_UART0 … #define PERIC_PCLK_UART0 … #define PERIC_SCLK_UART1 … #define PERIC_PCLK_UART1 … #define PERIC_DMA0_IPCLKPORT_ACLK … #define PERIC_DMA1_IPCLKPORT_ACLK … #define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 … #define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 … #define PERIC_PCLK_SPI0 … #define PERIC_SCLK_SPI0 … #define PERIC_PCLK_SPI1 … #define PERIC_SCLK_SPI1 … #define PERIC_PCLK_SPI2 … #define PERIC_SCLK_SPI2 … #define PERIC_PCLK_TDM0 … #define PERIC_PCLK_HSI2C0 … #define PERIC_PCLK_HSI2C1 … #define PERIC_PCLK_HSI2C2 … #define PERIC_PCLK_HSI2C3 … #define PERIC_PCLK_HSI2C4 … #define PERIC_PCLK_HSI2C5 … #define PERIC_PCLK_HSI2C6 … #define PERIC_PCLK_HSI2C7 … #define PERIC_MCAN0_IPCLKPORT_CCLK … #define PERIC_MCAN0_IPCLKPORT_PCLK … #define PERIC_MCAN1_IPCLKPORT_CCLK … #define PERIC_MCAN1_IPCLKPORT_PCLK … #define PERIC_MCAN2_IPCLKPORT_CCLK … #define PERIC_MCAN2_IPCLKPORT_PCLK … #define PERIC_MCAN3_IPCLKPORT_CCLK … #define PERIC_MCAN3_IPCLKPORT_PCLK … #define PERIC_PCLK_ADCIF … #define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I … #define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I … #define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I … #define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I … #define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I … #define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK … #define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK … #define PERIC_HCLK_TDM0 … #define PERIC_PCLK_TDM1 … #define PERIC_HCLK_TDM1 … #define PERIC_EQOS_PHYRXCLK_MUX … #define PERIC_EQOS_PHYRXCLK … #define PERIC_DOUT_RGMII_CLK … #define PERIC_NR_CLK … /* FSYS0 */ #define UFS0_MPHY_REFCLK_IXTAL24 … #define UFS0_MPHY_REFCLK_IXTAL26 … #define UFS1_MPHY_REFCLK_IXTAL24 … #define UFS1_MPHY_REFCLK_IXTAL26 … #define UFS0_TOP0_HCLK_BUS … #define UFS0_TOP0_ACLK … #define UFS0_TOP0_CLK_UNIPRO … #define UFS0_TOP0_FMP_CLK … #define UFS1_TOP1_HCLK_BUS … #define UFS1_TOP1_ACLK … #define UFS1_TOP1_CLK_UNIPRO … #define UFS1_TOP1_FMP_CLK … #define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC … #define PCIE_SUBCTRL_INST0_AUX_CLK_SOC … #define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC … #define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC … #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I … #define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I … #define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I … #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I … #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I … #define FSYS0_DOUT_FSYS0_PERIBUS_GRP … #define FSYS0_NR_CLK … /* FSYS1 */ #define PCIE_LINK0_IPCLKPORT_DBI_ACLK … #define PCIE_LINK0_IPCLKPORT_AUX_ACLK … #define PCIE_LINK0_IPCLKPORT_MSTR_ACLK … #define PCIE_LINK0_IPCLKPORT_SLV_ACLK … #define PCIE_LINK1_IPCLKPORT_DBI_ACLK … #define PCIE_LINK1_IPCLKPORT_AUX_ACLK … #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK … #define PCIE_LINK1_IPCLKPORT_SLV_ACLK … #define FSYS1_NR_CLK … /* IMEM */ #define IMEM_DMA0_IPCLKPORT_ACLK … #define IMEM_DMA1_IPCLKPORT_ACLK … #define IMEM_WDT0_IPCLKPORT_PCLK … #define IMEM_WDT1_IPCLKPORT_PCLK … #define IMEM_WDT2_IPCLKPORT_PCLK … #define IMEM_MCT_PCLK … #define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS … #define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS … #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS … #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS … #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS … #define IMEM_NR_CLK … /* MFC */ #define MFC_MFC_IPCLKPORT_ACLK … #define MFC_NR_CLK … /* CAM_CSI */ #define CAM_CSI0_0_IPCLKPORT_I_ACLK … #define CAM_CSI0_1_IPCLKPORT_I_ACLK … #define CAM_CSI0_2_IPCLKPORT_I_ACLK … #define CAM_CSI0_3_IPCLKPORT_I_ACLK … #define CAM_CSI1_0_IPCLKPORT_I_ACLK … #define CAM_CSI1_1_IPCLKPORT_I_ACLK … #define CAM_CSI1_2_IPCLKPORT_I_ACLK … #define CAM_CSI1_3_IPCLKPORT_I_ACLK … #define CAM_CSI2_0_IPCLKPORT_I_ACLK … #define CAM_CSI2_1_IPCLKPORT_I_ACLK … #define CAM_CSI2_2_IPCLKPORT_I_ACLK … #define CAM_CSI2_3_IPCLKPORT_I_ACLK … #define CAM_CSI_NR_CLK … #endif /*_DT_BINDINGS_CLOCK_FSD_H */
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