/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2021 SiFive, Inc. * Copyright (C) 2018-2019 Wesley Terpstra * Copyright (C) 2018-2019 Paul Walmsley * Copyright (C) 2020-2021 Zong Li * * The FU540 PRCI implements clock and reset control for the SiFive * FU540-C000 chip. This driver assumes that it has sole control * over all PRCI resources. * * This driver is based on the PRCI driver written by Wesley Terpstra: * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 * * References: * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ #ifndef __SIFIVE_CLK_FU540_PRCI_H #define __SIFIVE_CLK_FU540_PRCI_H #include <linux/module.h> #include <dt-bindings/clock/sifive-fu540-prci.h> #include "sifive-prci.h" /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = …; static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = …; static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = …; /* Linux clock framework integration */ static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = …; static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = …; static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = …; /* List of clock controls provided by the PRCI */ static struct __prci_clock __prci_init_clocks_fu540[] = …; static const struct prci_clk_desc prci_clk_fu540 = …; #endif /* __SIFIVE_CLK_FU540_PRCI_H */