linux/drivers/clk/socfpga/clk-pll-a10.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Altera Corporation. All rights reserved
 */
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "clk.h"

/* Clock Manager offsets */
#define CLK_MGR_PLL_CLK_SRC_SHIFT …
#define CLK_MGR_PLL_CLK_SRC_MASK …

/* Clock bypass bits */
#define SOCFPGA_PLL_BG_PWRDWN …
#define SOCFPGA_PLL_PWR_DOWN …
#define SOCFPGA_PLL_EXT_ENA …
#define SOCFPGA_PLL_DIVF_MASK …
#define SOCFPGA_PLL_DIVF_SHIFT …
#define SOCFPGA_PLL_DIVQ_MASK …
#define SOCFPGA_PLL_DIVQ_SHIFT …
#define SOCFGPA_MAX_PARENTS …

#define SOCFPGA_MAIN_PLL_CLK …
#define SOCFPGA_PERIP_PLL_CLK …

#define to_socfpga_clk(p) …

void __iomem *clk_mgr_a10_base_addr;

static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{ … }

static u8 clk_pll_get_parent(struct clk_hw *hwclk)
{ … }

static const struct clk_ops clk_pll_ops = …;

static void __init __socfpga_pll_init(struct device_node *node,
				      const struct clk_ops *ops)
{ … }

void __init socfpga_a10_pll_init(struct device_node *node)
{ … }